STM32F4_RCC_DCKCFGR
STM32F4_RCC_DCKCFGR, 20, 3,
STM32F4_RCC_DCKCFGR, 22, 3,
STM32F4_RCC_DCKCFGR, 20, 3,
STM32F4_RCC_DCKCFGR, 22, 3,
STM32F4_RCC_DCKCFGR, 27, 1,
STM32F4_RCC_DCKCFGR, 28, 1,
STM32F4_RCC_DCKCFGR, 29, 1,
STM32F4_RCC_DCKCFGR, 20, 3,
STM32F4_RCC_DCKCFGR, 22, 3,
STM32F4_RCC_DCKCFGR, 20, 3,
STM32F4_RCC_DCKCFGR, 22, 3,
STM32F4_RCC_DCKCFGR, 25, 1,
STM32F4_RCC_DCKCFGR, 26, 1,
CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 0, 5, 0, NULL},
CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 8, 5, 0, NULL },
STM32F4_RCC_DCKCFGR, 16, 2, 0, post_divr_table },