STM32F4_RCC_CFGR
STM32F4_RCC_CFGR, 23, 1,
STM32F4_RCC_CFGR, 23, 1,
STM32F4_RCC_CFGR, 23, 1,
STM32F4_RCC_CFGR, 23, 1,
base + STM32F4_RCC_CFGR, 0, 3, 0, NULL, &stm32f4_clk_lock);
CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
0, base + STM32F4_RCC_CFGR, 16, 5, 0,
if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx))
if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx))