SR_ARR
SR_ARR(GSL_SOURCE_SELECT, inst), \
SR_ARR(HDMI_STREAM_ENC_CLOCK_CONTROL, id), \
SR_ARR(HDMI_STREAM_ENC_INPUT_MUX_CONTROL, id), \
SR_ARR(HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, id), \
SR_ARR(HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2, id)
SR_ARR(HDMI_TB_ENC_CONTROL, id), SR_ARR(HDMI_TB_ENC_H_ACTIVE_BLANK, id), \
SR_ARR(HDMI_TB_ENC_HC_ACTIVE_BLANK, id), SR_ARR(HDMI_TB_ENC_MODE, id), \
SR_ARR(HDMI_TB_ENC_PACKET_CONTROL, id), \
SR_ARR(HDMI_TB_ENC_DB_CONTROL, id), \
SR_ARR(HDMI_TB_ENC_PIXEL_FORMAT, id), \
SR_ARR(HDMI_TB_ENC_VBI_PACKET_CONTROL1, id), \
SR_ARR(HDMI_TB_ENC_GC_CONTROL, id), \
SR_ARR(HDMI_TB_ENC_GENERIC_PACKET_CONTROL0, id), \
SR_ARR(HDMI_TB_ENC_GENERIC_PACKET_CONTROL1, id), \
SR_ARR(HDMI_TB_ENC_GENERIC_PACKET0_1_LINE, id), \
SR_ARR(HDMI_TB_ENC_GENERIC_PACKET2_3_LINE, id), \
SR_ARR(HDMI_TB_ENC_GENERIC_PACKET4_5_LINE, id), \
SR_ARR(HDMI_TB_ENC_GENERIC_PACKET6_7_LINE, id), \
SR_ARR(HDMI_TB_ENC_GENERIC_PACKET8_9_LINE, id), \
SR_ARR(HDMI_TB_ENC_GENERIC_PACKET10_11_LINE, id), \
SR_ARR(HDMI_TB_ENC_GENERIC_PACKET12_13_LINE, id), \
SR_ARR(HDMI_TB_ENC_GENERIC_PACKET14_LINE, id), \
SR_ARR(HDMI_TB_ENC_ACR_PACKET_CONTROL, id), \
SR_ARR(HDMI_TB_ENC_ACR_32_0, id), SR_ARR(HDMI_TB_ENC_ACR_32_1, id), \
SR_ARR(HDMI_TB_ENC_ACR_44_0, id), SR_ARR(HDMI_TB_ENC_ACR_44_1, id), \
SR_ARR(HDMI_TB_ENC_ACR_48_0, id), SR_ARR(HDMI_TB_ENC_ACR_48_1, id), \
SR_ARR(HDMI_TB_ENC_CRC_CNTL, id), \
SR_ARR(HDMI_TB_ENC_METADATA_PACKET_CONTROL, id)
SR_ARR(HDMI_LINK_ENC_CLK_CTRL, id), \
SR_ARR(HDMI_LINK_ENC_CONTROL, id), \
SR_ARR(HDMI_FRL_ENC_CONFIG, id), \
SR_ARR(HDMI_FRL_ENC_CONFIG2, id),\
SR_ARR(HDMI_FRL_ENC_MEM_CTRL, id)
SR_ARR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS, id), \
SR_ARR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES, id), \
SR_ARR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, id), \
SR_ARR(DCCG_AUDIO_DTO_SOURCE, id), SR_ARR(DCCG_AUDIO_DTO0_MODULE, id), \
SR_ARR(DCCG_AUDIO_DTO0_PHASE, id), SR_ARR(DCCG_AUDIO_DTO1_MODULE, id), \
SR_ARR(DCCG_AUDIO_DTO1_PHASE, id) \
SR_ARR(DIO_LINKA_CNTL, id), SR_ARR(DIO_LINKB_CNTL, id), \
SR_ARR(DIO_LINKC_CNTL, id), SR_ARR(DIO_LINKD_CNTL, id), \
SR_ARR(DIO_LINKE_CNTL, id), SR_ARR(DIO_LINKF_CNTL, id)
SR_ARR(DP_STREAM_MAPPER_CONTROL0, id), \
SR_ARR(DP_STREAM_MAPPER_CONTROL1, id), \
SR_ARR(DP_STREAM_MAPPER_CONTROL2, id), \
SR_ARR(DP_STREAM_MAPPER_CONTROL3, id), \
SR_ARR(DWB_ENABLE_CLK_CTRL, id), SR_ARR(DWB_MEM_PWR_CTRL, id), \
SR_ARR(FC_MODE_CTRL, id), SR_ARR(FC_FLOW_CTRL, id), \
SR_ARR(FC_WINDOW_START, id), SR_ARR(FC_WINDOW_SIZE, id), \
SR_ARR(FC_SOURCE_SIZE, id), SR_ARR(DWB_UPDATE_CTRL, id), \
SR_ARR(DWB_CRC_CTRL, id), SR_ARR(DWB_CRC_MASK_R_G, id), \
SR_ARR(DWB_CRC_MASK_B_A, id), SR_ARR(DWB_CRC_VAL_R_G, id), \
SR_ARR(DWB_CRC_VAL_B_A, id), SR_ARR(DWB_OUT_CTRL, id), \
SR_ARR(DWB_MMHUBBUB_BACKPRESSURE_CNT_EN, id), \
SR_ARR(DWB_MMHUBBUB_BACKPRESSURE_CNT, id), \
SR_ARR(DWB_HOST_READ_CONTROL, id), SR_ARR(DWB_SOFT_RESET, id), \
SR_ARR(DWB_HDR_MULT_COEF, id), SR_ARR(DWB_GAMUT_REMAP_MODE, id), \
SR_ARR(DWB_GAMUT_REMAP_COEF_FORMAT, id), \
SR_ARR(DWB_GAMUT_REMAPA_C11_C12, id), \
SR_ARR(DWB_GAMUT_REMAPA_C13_C14, id), \
SR_ARR(DWB_GAMUT_REMAPA_C21_C22, id), \
SR_ARR(DWB_GAMUT_REMAPA_C23_C24, id), \
SR_ARR(DWB_GAMUT_REMAPA_C31_C32, id), \
SR_ARR(DWB_GAMUT_REMAPA_C33_C34, id), \
SR_ARR(DWB_GAMUT_REMAPB_C11_C12, id), \
SR_ARR(DWB_GAMUT_REMAPB_C13_C14, id), \
SR_ARR(DWB_GAMUT_REMAPB_C21_C22, id), \
SR_ARR(DWB_GAMUT_REMAPB_C23_C24, id), \
SR_ARR(DWB_GAMUT_REMAPB_C31_C32, id), \
SR_ARR(DWB_GAMUT_REMAPB_C33_C34, id), SR_ARR(DWB_OGAM_CONTROL, id), \
SR_ARR(DWB_OGAM_LUT_INDEX, id), SR_ARR(DWB_OGAM_LUT_DATA, id), \
SR_ARR(DWB_OGAM_LUT_CONTROL, id), \
SR_ARR(DWB_OGAM_RAMA_START_CNTL_B, id), \
SR_ARR(DWB_OGAM_RAMA_START_CNTL_G, id), \
SR_ARR(DWB_OGAM_RAMA_START_CNTL_R, id), \
SR_ARR(DWB_OGAM_RAMA_START_BASE_CNTL_B, id), \
SR_ARR(DWB_OGAM_RAMA_START_SLOPE_CNTL_B, id), \
SR_ARR(DWB_OGAM_RAMA_START_BASE_CNTL_G, id), \
SR_ARR(DWB_OGAM_RAMA_START_SLOPE_CNTL_G, id), \
SR_ARR(DWB_OGAM_RAMA_START_BASE_CNTL_R, id), \
SR_ARR(DWB_OGAM_RAMA_START_SLOPE_CNTL_R, id), \
SR_ARR(DWB_OGAM_RAMA_END_CNTL1_B, id), \
SR_ARR(DWB_OGAM_RAMA_END_CNTL2_B, id), \
SR_ARR(DWB_OGAM_RAMA_END_CNTL1_G, id), \
SR_ARR(DWB_OGAM_RAMA_END_CNTL2_G, id), \
SR_ARR(DWB_OGAM_RAMA_END_CNTL1_R, id), \
SR_ARR(DWB_OGAM_RAMA_END_CNTL2_R, id), \
SR_ARR(DWB_OGAM_RAMA_OFFSET_B, id), SR_ARR(DWB_OGAM_RAMA_OFFSET_G, id), \
SR_ARR(DWB_OGAM_RAMA_OFFSET_R, id), \
SR_ARR(DWB_OGAM_RAMA_REGION_0_1, id), \
SR_ARR(DWB_OGAM_RAMA_REGION_2_3, id), \
SR_ARR(DWB_OGAM_RAMA_REGION_4_5, id), \
SR_ARR(DWB_OGAM_RAMA_REGION_6_7, id), \
SR_ARR(DWB_OGAM_RAMA_REGION_8_9, id), \
SR_ARR(DWB_OGAM_RAMA_REGION_10_11, id), \
SR_ARR(DWB_OGAM_RAMA_REGION_12_13, id), \
SR_ARR(DWB_OGAM_RAMA_REGION_14_15, id), \
SR_ARR(DWB_OGAM_RAMA_REGION_16_17, id), \
SR_ARR(DWB_OGAM_RAMA_REGION_18_19, id), \
SR_ARR(DWB_OGAM_RAMA_REGION_20_21, id), \
SR_ARR(DWB_OGAM_RAMA_REGION_22_23, id), \
SR_ARR(DWB_OGAM_RAMA_REGION_24_25, id), \
SR_ARR(DWB_OGAM_RAMA_REGION_26_27, id), \
SR_ARR(DWB_OGAM_RAMA_REGION_28_29, id), \
SR_ARR(DWB_OGAM_RAMA_REGION_30_31, id), \
SR_ARR(DWB_OGAM_RAMA_REGION_32_33, id), \
SR_ARR(DWB_OGAM_RAMB_START_CNTL_B, id), \
SR_ARR(DWB_OGAM_RAMB_START_CNTL_G, id), \
SR_ARR(DWB_OGAM_RAMB_START_CNTL_R, id), \
SR_ARR(DWB_OGAM_RAMB_START_BASE_CNTL_B, id), \
SR_ARR(DWB_OGAM_RAMB_START_SLOPE_CNTL_B, id), \
SR_ARR(DWB_OGAM_RAMB_START_BASE_CNTL_G, id), \
SR_ARR(DWB_OGAM_RAMB_START_SLOPE_CNTL_G, id), \
SR_ARR(DWB_OGAM_RAMB_START_BASE_CNTL_R, id), \
SR_ARR(DWB_OGAM_RAMB_START_SLOPE_CNTL_R, id), \
SR_ARR(DWB_OGAM_RAMB_END_CNTL1_B, id), \
SR_ARR(DWB_OGAM_RAMB_END_CNTL2_B, id), \
SR_ARR(DWB_OGAM_RAMB_END_CNTL1_G, id), \
SR_ARR(DWB_OGAM_RAMB_END_CNTL2_G, id), \
SR_ARR(DWB_OGAM_RAMB_END_CNTL1_R, id), \
SR_ARR(DWB_OGAM_RAMB_END_CNTL2_R, id), \
SR_ARR(DWB_OGAM_RAMB_OFFSET_B, id), SR_ARR(DWB_OGAM_RAMB_OFFSET_G, id), \
SR_ARR(DWB_OGAM_RAMB_OFFSET_R, id), \
SR_ARR(DWB_OGAM_RAMB_REGION_0_1, id), \
SR_ARR(DWB_OGAM_RAMB_REGION_2_3, id), \
SR_ARR(DWB_OGAM_RAMB_REGION_4_5, id), \
SR_ARR(DWB_OGAM_RAMB_REGION_6_7, id), \
SR_ARR(DWB_OGAM_RAMB_REGION_8_9, id), \
SR_ARR(DWB_OGAM_RAMB_REGION_10_11, id), \
SR_ARR(DWB_OGAM_RAMB_REGION_12_13, id), \
SR_ARR(DWB_OGAM_RAMB_REGION_14_15, id), \
SR_ARR(DWB_OGAM_RAMB_REGION_16_17, id), \
SR_ARR(DWB_OGAM_RAMB_REGION_18_19, id), \
SR_ARR(DWB_OGAM_RAMB_REGION_20_21, id), \
SR_ARR(DWB_OGAM_RAMB_REGION_22_23, id), \
SR_ARR(DWB_OGAM_RAMB_REGION_24_25, id), \
SR_ARR(DWB_OGAM_RAMB_REGION_26_27, id), \
SR_ARR(DWB_OGAM_RAMB_REGION_28_29, id), \
SR_ARR(DWB_OGAM_RAMB_REGION_30_31, id), \
SR_ARR(DWB_OGAM_RAMB_REGION_32_33, id)
SR_ARR(DIO_LINKA_CNTL, id), \
SR_ARR(DIO_LINKB_CNTL, id), \
SR_ARR(DIO_LINKC_CNTL, id), \
SR_ARR(DIO_LINKD_CNTL, id), \
SR_ARR(DIO_LINKE_CNTL, id), \
SR_ARR(DIO_LINKF_CNTL, id),\
SR_ARR(DIO_CLK_CNTL, id)
SR_ARR(GSL_SOURCE_SELECT, inst),\
SR_ARR(DIO_CLK_CNTL, id)
SR_ARR(GSL_SOURCE_SELECT, inst), \
SR_ARR(DP_STREAM_MAPPER_CONTROL0, id), \
SR_ARR(DP_STREAM_MAPPER_CONTROL1, id), \
SR_ARR(DP_STREAM_MAPPER_CONTROL2, id), \
SR_ARR(DP_STREAM_MAPPER_CONTROL3, id), \
SR_ARR(HDMI_STREAM_ENC_AUDIO_CONTROL, id),\
SR_ARR(HDMI_TB_ENC_MEM_CTRL, id),\
SR_ARR(HDMI_FRL_ENC_MEM_CTRL, id)
SR_ARR(GSL_SOURCE_SELECT, inst), \
SR_ARR(OTG_PIXEL_RATE_DIV, index)
SR_ARR(DP_STREAM_MAPPER_CONTROL0, id), \
SR_ARR(DP_STREAM_MAPPER_CONTROL1, id), \
SR_ARR(DP_STREAM_MAPPER_CONTROL2, id), \
SR_ARR(DP_STREAM_MAPPER_CONTROL3, id), \
SR_ARR(GSL_SOURCE_SELECT, inst), \