STATUS_REG
if (readl(trng->mem + STATUS_REG) != TRNG_SUCCESSFUL_STARTUP) {
if (readl(trng->mem + STATUS_REG) == TRNG_FAILED_STARTUP) {
if (readl(trng->mem + STATUS_REG) == TRNG_NEW_RAND_AVAILABLE) {
if (readl(trng->mem + STATUS_REG) != TRNG_ACK_RESET) {
if (readl(trng->mem + STATUS_REG) != TRNG_ACK_RESET) {
status = inw(dev->iobase + STATUS_REG);
status = inw(dev->iobase + STATUS_REG);
int id = ID_BITS(inw(dev->iobase + STATUS_REG));
if ((DCAL_BIT & inw(dev->iobase + STATUS_REG)) == 0)
writel_relaxed(1, kbd->io_base + STATUS_REG);
sts = readl_relaxed(kbd->io_base + STATUS_REG);
writel_relaxed(0, kbd->io_base + STATUS_REG);
status = i2c_smbus_read_byte_data(client, STATUS_REG);
status_reg = i2c_smbus_read_byte_data(client, STATUS_REG);
val = i2c_smbus_read_byte_data(client, STATUS_REG);
ret = readl_poll_timeout(rnandc->regs + STATUS_REG, status,
if ((readl(config->ioaddr + STATUS_REG)) & STATUS_FAIL)
status = readl(config->ioaddr + STATUS_REG);
irq_data = readl(config->ioaddr + STATUS_REG);
val = readl(config->ioaddr + STATUS_REG);
writel(val, config->ioaddr + STATUS_REG);
err = NCR5380_poll_politely(hostdata, STATUS_REG, SR_BSY, SR_BSY,
if ((NCR5380_read(STATUS_REG) & (SR_SEL | SR_IO)) == (SR_SEL | SR_IO)) {
err = NCR5380_poll_politely(hostdata, STATUS_REG, SR_REQ, SR_REQ, HZ);
if (NCR5380_poll_politely(hostdata, STATUS_REG, SR_REQ | SR_BSY,
if ((NCR5380_read(STATUS_REG) & PHASE_MASK) != p) {
STATUS_REG, SR_REQ, 0, 5 * HZ * can_sleep) < 0)
tmp = NCR5380_read(STATUS_REG);
PHASE_SR_TO_TCR(NCR5380_read(STATUS_REG) & PHASE_MASK));
rc = NCR5380_poll_politely(hostdata, STATUS_REG, SR_REQ, SR_REQ,
tmp = NCR5380_read(STATUS_REG) & PHASE_MASK;
rc = NCR5380_poll_politely(hostdata, STATUS_REG, SR_REQ, 0,
if ((tmp = (NCR5380_read(STATUS_REG) & PHASE_MASK)) != p) {
if (!NCR5380_poll_politely(hostdata, STATUS_REG,
tmp = NCR5380_read(STATUS_REG);
while (NCR5380_read(STATUS_REG) & SR_REQ)
err = NCR5380_poll_politely(hostdata, STATUS_REG,
!(NCR5380_read(STATUS_REG) & SR_BSY)) {
STATUS_REG, SR_SEL, 0, 0) < 0) {
STATUS_REG, SR_REQ, SR_REQ, 0) < 0) {
if ((NCR5380_read(STATUS_REG) & (SR_BSY | SR_SEL)) == 0)
status = NCR5380_read(STATUS_REG);
status = NCR5380_read(STATUS_REG);
NCR5380_read(STATUS_REG);
for (pass = 1; (NCR5380_read(STATUS_REG) & SR_BSY) && pass <= 6; ++pass) {
STATUS_REG, SR_BSY, 0, 5 * HZ);
if ((NCR5380_read(STATUS_REG) & PHASE_MASK) == p && (p & SR_IO)) {
unsigned char sr = NCR5380_read(STATUS_REG);
PHASE_SR_TO_TCR(NCR5380_read(STATUS_REG) & PHASE_MASK));
(STATUS_REG << 4))) {