SRC_TOP5
{ SRC_TOP5, 0, BIT(0) }, /* MUX mout_user_aclk400_disp1 */
{ SRC_TOP5, 0, BIT(24) }, /* MUX mout_user_aclk300_disp1 */
{ SRC_TOP5, 0, BIT(28) }, /* MUX mout_user_aclk300_gscl */
{ SRC_TOP5, 0, BIT(16) }, /* MUX mout_user_aclk_g3d */
SRC_TOP5,
mout_user_aclk400_disp1_p, SRC_TOP5, 0, 1),
SRC_TOP5, 4, 1),
SRC_TOP5, 8, 1),
SRC_TOP5, 12, 1),
SRC_TOP5, 16, 1, CLK_SET_RATE_PARENT, 0),
SRC_TOP5, 20, 1),
mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1),
mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1),