SS_VECTOR
{ SVM_EXIT_EXCP_BASE + SS_VECTOR, "SS excp" }, \
err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
return emulate_exception(ctxt, SS_VECTOR, err, true);
SS_VECTOR : GP_VECTOR,
case SS_VECTOR:
if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
case SS_VECTOR:
BIT(NP_VECTOR) | BIT(SS_VECTOR) | BIT(GP_VECTOR) |
{ SVM_EXIT_EXCP_BASE + SS_VECTOR, "SS excp" }, \
svm_run_l2(svm, l2_ss_pending_test, SS_VECTOR, SS_ERROR_CODE);
GUEST_ASSERT_EQ(vector == SS_VECTOR ? vmlaunch() : vmresume(), 0);
vmx_run_l2(l2_ss_pending_test, SS_VECTOR, (u16)SS_ERROR_CODE);
events.exception.nr = SS_VECTOR;
assert_ucall_vector(vcpu, SS_VECTOR);
TEST_ASSERT_EQ(events.exception.nr, SS_VECTOR);
#define GP_ERROR_CODE_AMD ((SS_VECTOR * 8) | ERROR_CODE_IDT_FLAG)
#define GP_ERROR_CODE_INTEL ((SS_VECTOR * 8) | ERROR_CODE_IDT_FLAG | ERROR_CODE_EXT_FLAG)
#define INTERCEPT_SS (BIT_ULL(SS_VECTOR))
GUEST_SYNC(SS_VECTOR);