SSP_WRITE_BITS
SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay,
SSP_WRITE_BITS(chip->cr0, chip_info->duplex,
SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len,
SSP_WRITE_BITS(chip->cr0, chip_info->iface,
SSP_WRITE_BITS(chip->cr1, chip_info->wait_state,
SSP_WRITE_BITS(chip->cr0, bits - 1,
SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4);
SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5);
SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig,
SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig,
SSP_WRITE_BITS(chip->cr0, bits - 1,
SSP_WRITE_BITS(chip->cr0, chip_info->iface,
SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6);
SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7);
SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8);
SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0);
SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1);
SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2);
SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD,