drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h

73

.name = "sspp_2", .id = SSPP_VIG2,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h

74

.name = "sspp_2", .id = SSPP_VIG2,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h

80

.name = "sspp_2", .id = SSPP_VIG2,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h

72

.name = "sspp_2", .id = SSPP_VIG2,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h

79

.name = "sspp_2", .id = SSPP_VIG2,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h

79

.name = "sspp_2", .id = SSPP_VIG2,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h

82

.name = "sspp_2", .id = SSPP_VIG2,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h

85

.name = "sspp_2", .id = SSPP_VIG2,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h

85

.name = "sspp_2", .id = SSPP_VIG2,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h

84

.name = "sspp_2", .id = SSPP_VIG2,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h

84

.name = "sspp_2", .id = SSPP_VIG2,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h

83

.name = "sspp_2", .id = SSPP_VIG2,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h

84

.name = "sspp_2", .id = SSPP_VIG2,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h

83

.name = "sspp_2", .id = SSPP_VIG2,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h

73

.name = "sspp_2", .id = SSPP_VIG2,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h

73

.name = "sspp_2", .id = SSPP_VIG2,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h

72

.name = "sspp_2", .id = SSPP_VIG2,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

199

case SSPP_VIG2:

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

491

[SSPP_VIG2] = { { 0, 6, 4 }, { 3, 8 } },

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c

203

status->sspp[SSPP_VIG2] = (value >> 8) & 0x1;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c

91

status->sspp[SSPP_VIG2] = (value >> 8) & 0x3;

drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c

198

[SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,

drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c

28

[SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,

drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c

287

[SSPP_VIG2] = 7, [SSPP_VIG3] = 19,

drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c

539

[SSPP_VIG2] = 7, [SSPP_VIG3] = 19,

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c

295

case SSPP_VIG2: return MDP5_CTL_LAYER_REG_VIG2(stage);

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c

318

case SSPP_VIG2: return MDP5_CTL_LAYER_EXT_REG_VIG2_BIT3;

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c

446

case SSPP_VIG2: return MDP5_CTL_FLUSH_VIG2;

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

607

SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3,