drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

454

DECLARE_BITMAP(active_fetch, SSPP_MAX);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

455

DECLARE_BITMAP(active_pipes, SSPP_MAX);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

488

[SSPP_MAX] = { { -1 }, { -1 } },

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

65

static const u32 fetch_tbl[SSPP_MAX] = {CTL_INVALID_BIT, 16, 17, 18, 19,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

744

for (i = 0; i < SSPP_MAX; i++) {

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

761

for (i = 0; i < SSPP_MAX; i++) {

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h

52

u8 sspp[SSPP_MAX];

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

281

for (i = SSPP_NONE; i < SSPP_MAX; i++) {

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

92

for (i = SSPP_VIG0; i < SSPP_MAX; i++)

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h

134

uint32_t sspp_to_crtc_id[SSPP_MAX - SSPP_NONE];

drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h

39

struct dpu_hw_sspp *hw_sspp[SSPP_MAX - SSPP_NONE];

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h

28

struct mdp5_hw_pipe *hwpipes[SSPP_MAX];

drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.h

33

struct drm_plane *hwpipe_to_plane[SSPP_MAX];

drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c

26

u32 pipe_reqprio_fifo_wm0[SSPP_MAX];

drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c

27

u32 pipe_reqprio_fifo_wm1[SSPP_MAX];

drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c

28

u32 pipe_reqprio_fifo_wm2[SSPP_MAX];