BEACON_QUEUE
ring = &rtlpci->tx_ring[BEACON_QUEUE];
rtlpriv->cfg->ops->tx_polling(hw, BEACON_QUEUE);
ring = &rtlpci->tx_ring[BEACON_QUEUE];
BEACON_QUEUE, &tcb_desc);
rtlpci->txringcount[BEACON_QUEUE] = 2;
if (hw_queue != BEACON_QUEUE) {
if (own == 1 && hw_queue != BEACON_QUEUE) {
hw_queue != BEACON_QUEUE) {
if (queue_len == 0 || queue_id == BEACON_QUEUE ||
return BEACON_QUEUE;
struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
if (queue_id == BEACON_QUEUE ||
if (hw_queue == BEACON_QUEUE) {
((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
if (queue_id == BEACON_QUEUE ||
if (hw_queue == BEACON_QUEUE) {
queue_id == BEACON_QUEUE) {
ring = &rtlpci->tx_ring[BEACON_QUEUE];
rtlpriv->cfg->ops->tx_polling(hw, BEACON_QUEUE);
rtlpci->tx_ring[BEACON_QUEUE].dma);
queue_id == BEACON_QUEUE) {
if (hw_queue == BEACON_QUEUE)
((u64)rtlpci->tx_ring[BEACON_QUEUE].buffer_desc_dma) >>
((u64)rtlpci->tx_ring[BEACON_QUEUE].buffer_desc_dma) &
if (queue_id == BEACON_QUEUE ||
if (hw_queue == BEACON_QUEUE)
case BEACON_QUEUE:
if (queue_index < BEACON_QUEUE) {
if (queue_index < BEACON_QUEUE) {
if (q_idx == BEACON_QUEUE) {
rtl_write_dword(rtlpriv, TBDA, rtlpci->tx_ring[BEACON_QUEUE].dma);
queue_id == BEACON_QUEUE) {
((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
if (queue_id == BEACON_QUEUE ||
if (hw_queue == BEACON_QUEUE) {
struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
if (queue_id == BEACON_QUEUE ||
if (hw_queue == BEACON_QUEUE) {
rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32));
struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32));
if (queue_id == BEACON_QUEUE ||
if (hw_queue == BEACON_QUEUE) {