SSISR
RSND_GEN_M_REG(SSISR, 0x04, 0x40),
rsnd_mod_write(mod, SSISR, 0);
return rsnd_mod_read(mod, SSISR);
rz_ssi_reg_mask_setl(ssi, SSISR,
ret = readl_poll_timeout_atomic(ssi->base + SSISR, tmp, (tmp & SSISR_IIRQ), 1, 100);
rz_ssi_reg_mask_setl(ssi, SSISR,
u32 ssisr = rz_ssi_reg_readl(ssi, SSISR);
rz_ssi_reg_mask_setl(ssi, SSISR, SSISR_TOIRQ | SSISR_TUIRQ |