BDW_DSP_BAR
snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR,
snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR,
snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR,
snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR,
snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CLKCTL,
snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR2,
snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_HMDC,
snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_IMRX,
snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_IMRD,
snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCX, 0x0);
snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCD, 0x0);
snd_sof_dsp_write(sdev, BDW_DSP_BAR, 0x80, 0x6);
snd_sof_dsp_write(sdev, BDW_DSP_BAR, 0xe0, 0x300a);
status = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCD);
panic = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCX);
imrx = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IMRX);
imrd = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IMRD);
isr = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_ISRX);
imrx = snd_sof_dsp_read64(sdev, BDW_DSP_BAR, SHIM_IMRX);
ipcx = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCX);
snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR,
ipcd = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCD);
snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR,
snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCX, SHIM_IPCX_BUSY);
snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IPCD,
snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IMRX,
snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IPCX,
snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IMRX,
sdev->bar[BDW_DSP_BAR] = devm_ioremap(sdev->dev, base, size);
if (!sdev->bar[BDW_DSP_BAR]) {
dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BDW_DSP_BAR]);
sdev->mmio_bar = BDW_DSP_BAR;
sdev->mailbox_bar = BDW_DSP_BAR;
{"dmac0", BDW_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE,
{"dmac1", BDW_DSP_BAR, DMAC1_OFFSET, DMAC_SIZE,
{"ssp0", BDW_DSP_BAR, SSP0_OFFSET, SSP_SIZE,
{"ssp1", BDW_DSP_BAR, SSP1_OFFSET, SSP_SIZE,
{"iram", BDW_DSP_BAR, IRAM_OFFSET, BDW_IRAM_SIZE,
{"dram", BDW_DSP_BAR, DRAM_OFFSET, BDW_DRAM_SIZE,
{"shim", BDW_DSP_BAR, SHIM_OFFSET, SHIM_SIZE,
snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_HMDC,
snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR,