SRI2_ARR
SRI2_ARR(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst), \
SRI2_ARR(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst), \
SRI2_ARR(MCIF_WB_BUF_PITCH, MCIF_WB, inst), \
SRI2_ARR(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst), \
SRI2_ARR(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst), \
SRI2_ARR(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst), \
SRI2_ARR(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst), \
SRI2_ARR(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst), \
SRI2_ARR(MCIF_WB_BUF_3_STATUS2, MCIF_WB, inst), \
SRI2_ARR(MCIF_WB_BUF_4_STATUS, MCIF_WB, inst), \
SRI2_ARR(MCIF_WB_BUF_4_STATUS2, MCIF_WB, inst), \
SRI2_ARR(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst), \
SRI2_ARR(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst), \
SRI2_ARR(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst), \
SRI2_ARR(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst), \
SRI2_ARR(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst), \
SRI2_ARR(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst), \
SRI2_ARR(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst), \
SRI2_ARR(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst), \
SRI2_ARR(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst), \
SRI2_ARR(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst), \
SRI2_ARR(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst), \
SRI2_ARR(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MMHUBBUB, inst), \
SRI2_ARR(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst), \
SRI2_ARR(MCIF_WB_WATERMARK, MMHUBBUB, inst), \
SRI2_ARR(MCIF_WB_CLOCK_GATER_CONTROL, MCIF_WB, inst), \
SRI2_ARR(MCIF_WB_SELF_REFRESH_CONTROL, MCIF_WB, inst), \
SRI2_ARR(MULTI_LEVEL_QOS_CTRL, MCIF_WB, inst), \
SRI2_ARR(MCIF_WB_SECURITY_LEVEL, MCIF_WB, inst), \
SRI2_ARR(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst), \
SRI2_ARR(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst), \
SRI2_ARR(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB, inst), \
SRI2_ARR(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB, inst), \
SRI2_ARR(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB, inst), \
SRI2_ARR(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB, inst), \
SRI2_ARR(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB, inst), \
SRI2_ARR(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB, inst), \
SRI2_ARR(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB, inst), \
SRI2_ARR(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB, inst), \
SRI2_ARR(MCIF_WB_BUF_1_RESOLUTION, MCIF_WB, inst), \
SRI2_ARR(MCIF_WB_BUF_2_RESOLUTION, MCIF_WB, inst), \
SRI2_ARR(MCIF_WB_BUF_3_RESOLUTION, MCIF_WB, inst), \
SRI2_ARR(MCIF_WB_BUF_4_RESOLUTION, MCIF_WB, inst), \
SRI2_ARR(MMHUBBUB_MEM_PWR_CNTL, MMHUBBUB, inst), \
SRI2_ARR(MMHUBBUB_WARMUP_ADDR_REGION, MMHUBBUB, inst), \
SRI2_ARR(MMHUBBUB_WARMUP_BASE_ADDR_HIGH, MMHUBBUB, inst), \
SRI2_ARR(MMHUBBUB_WARMUP_BASE_ADDR_LOW, MMHUBBUB, inst), \
SRI2_ARR(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB, inst)
SRI2_ARR(MMHUBBUB_CLOCK_CNTL, MMHUBBUB, inst)
SRI2_ARR(OPTC_CLOCK_CONTROL, OPTC, inst),\
SRI2_ARR(OPP_TOP_CLK_CONTROL, OPP, id)