SR1B
viafb_write_reg_mask(SR1B, VIASR, 0, BIT1);
viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1);
viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6);
viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6);
viafb_write_reg_mask(SR1B, VIASR,
(viafb_read_reg(VIASR, SR1B) & BIT1) >> 1;
viafb_write_reg_mask(SR1B, VIASR,
{VIASR, SR1B, 0xFF, 0xF0}, /* Power Management Control 0 */
{VIASR, SR1B, 0xFF, 0xF0},
{VIASR, SR1B, 0xFF, 0xF0},
{VIASR, SR1B, 0xFF, 0xF0},