SR1A
viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);
viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1);
sr1a = (unsigned int)viafb_read_reg(VIASR, SR1A);
viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0);
viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);
viafb_write_reg(SR1A, VIASR, sr1a);
sr1a = viafb_read_reg(VIASR, SR1A);
viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0);
viafb_write_reg(SR1A, VIASR, sr1a);
{VIASR, SR1A, 0xFB, 0x08},
{VIASR, SR1A, 0xFB, 0x08},
{VIASR, SR1A, 0xFB, 0x08},
{VIASR, SR1A, 0xFB, 0x08},
{VIASR, SR1A, 0xFB, 0x82},
{VIASR, SR1A, 0xFF, 0x0a}, /* GFX PREQ threshold */