SR16
{IGA1_FIFO_THRESHOLD_REG_NUM, {{SR16, 0, 5}, {SR16, 7, 7} } },
viafb_write_reg_mask(SR16, VIASR, 0x80, BIT7);
viafb_write_reg_mask(SR16, VIASR, 0x80, BIT7);
{VIASR, SR16, 0xBF, 0x08},
{VIASR, SR16, 0xBF, 0x08},
{VIASR, SR16, 0xBF, 0x08},
{VIASR, SR16, 0xBF, 0x08},
{VIASR, SR16, 0xBF, 0x08},
{VIASR, SR16, 0xFF, 0x08}, /* Display FIFO threshold Control */