drivers/gpu/drm/i915/display/intel_sprite_regs.h

241

#define SP_FORMAT_YUV422 REG_FIELD_PREP(SP_FORMAT_MASK, 0)

drivers/gpu/drm/i915/display/intel_sprite_regs.h

242

#define SP_FORMAT_8BPP REG_FIELD_PREP(SP_FORMAT_MASK, 2)

drivers/gpu/drm/i915/display/intel_sprite_regs.h

243

#define SP_FORMAT_BGR565 REG_FIELD_PREP(SP_FORMAT_MASK, 5)

drivers/gpu/drm/i915/display/intel_sprite_regs.h

244

#define SP_FORMAT_BGRX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 6)

drivers/gpu/drm/i915/display/intel_sprite_regs.h

245

#define SP_FORMAT_BGRA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 7)

drivers/gpu/drm/i915/display/intel_sprite_regs.h

246

#define SP_FORMAT_RGBX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 8)

drivers/gpu/drm/i915/display/intel_sprite_regs.h

247

#define SP_FORMAT_RGBA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 9)

drivers/gpu/drm/i915/display/intel_sprite_regs.h

248

#define SP_FORMAT_BGRX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 10) /* CHV pipe B */

drivers/gpu/drm/i915/display/intel_sprite_regs.h

249

#define SP_FORMAT_BGRA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 11) /* CHV pipe B */

drivers/gpu/drm/i915/display/intel_sprite_regs.h

250

#define SP_FORMAT_RGBX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 14)

drivers/gpu/drm/i915/display/intel_sprite_regs.h

251

#define SP_FORMAT_RGBA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 15)