SPRCTL
intel_de_write_fw(display, SPRCTL(pipe), sprctl);
intel_de_write_fw(display, SPRCTL(pipe), 0);
error->ctl = intel_de_read(display, SPRCTL(crtc->pipe));
ret = intel_de_read(display, SPRCTL(plane->pipe)) & SPRITE_ENABLE;
info->ctrl_reg = SPRCTL(info->pipe);
vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
if (vgpu_vreg_t(vgpu, SPRCTL(pipe)) & PLANE_CTL_ASYNC_FLIP)
MMIO_D(SPRCTL(PIPE_A));
MMIO_D(SPRCTL(PIPE_B));
MMIO_D(SPRCTL(PIPE_C));