SPR
{"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {RT, SPR}},
{"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, 0, {RT, SPR}},
{"mfspr", X(31,339), X_MASK, COM, 0, {RT, SPR}},
{"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {SPR, RS}},
{"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, 0, {SPR, RS}},
{"mtspr", X(31,467), X_MASK, COM, 0, {SPR, RS}},
#define PMR SPR
#define TMR SPR
#define SPRBAT SPR + 1
if (res_cfg->type <= SPR) {
case SPR:
case SPR:
case SPR:
case SPR:
if (res_cfg->type == SPR)
.type = SPR,
ADM8211_CSR_READ(SPR); /* eeprom_delay */
u32 reg = ADM8211_CSR_READ(SPR);
ADM8211_CSR_WRITE(SPR, reg);
__le32 SPR; /* 0x48 CSR9 */
write_reg_le32(par->dc_regs, SPR, pitch);
tmp = read3X4(par, SPR) & 0x0F;