SPI_WRITE
return sja1105_xfer_buf(priv, SPI_WRITE, regs->cgu_idiv[port],
return sja1105_xfer_buf(priv, SPI_WRITE, regs->mii_tx_clk[port],
return sja1105_xfer_buf(priv, SPI_WRITE, regs->mii_rx_clk[port],
return sja1105_xfer_buf(priv, SPI_WRITE, regs->mii_ext_tx_clk[port],
return sja1105_xfer_buf(priv, SPI_WRITE, regs->mii_ext_rx_clk[port],
return sja1105_xfer_buf(priv, SPI_WRITE, regs->rgmii_tx_clk[port],
return sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_tx[port],
return sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_rx[port],
rc = sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_id[port],
return sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_id[port],
return sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_id[port],
return sja1105_xfer_buf(priv, SPI_WRITE, regs->rmii_ref_clk[port],
return sja1105_xfer_buf(priv, SPI_WRITE, regs->rmii_ext_tx_clk[port],
rc = sja1105_xfer_buf(priv, SPI_WRITE, regs->rmii_pll1, packed_buf,
rc = sja1105_xfer_buf(priv, SPI_WRITE, regs->rmii_pll1, packed_buf,
rc = sja1105_xfer_buf(priv, SPI_WRITE, SJA1110_BASE_TIMER_CLK,
return sja1105_xfer_buf(priv, SPI_WRITE, SJA1110_BASE_MCSS_CLK,
rc = sja1105_xfer_buf(priv, SPI_WRITE, ops->addr, packed_buf,
cmd.rdwrset = SPI_WRITE; /* Action is write */
rc = sja1105_xfer_buf(priv, SPI_WRITE, ops->addr, packed_buf,
rc = sja1105_xfer_u32(priv, SPI_WRITE,
return sja1105_xfer_u32(priv, SPI_WRITE, regs->pcs_base[phy] + offset,
rc = sja1105_xfer_u32(priv, SPI_WRITE, addr, ®, NULL);
return sja1105_xfer_u32(priv, SPI_WRITE, addr, &tmp, NULL);
rc = sja1105_xfer_u32(priv, SPI_WRITE, addr, ®, NULL);
return sja1105_xfer_u32(priv, SPI_WRITE, addr, &tmp, NULL);
return sja1105_xfer_u32(priv, SPI_WRITE, regs->mdio_100base_tx + reg,
return sja1105_xfer_u32(priv, SPI_WRITE, addr, &tmp, NULL);
rc = sja1105_xfer_u32(priv, SPI_WRITE,
if (rw == SPI_WRITE)
return sja1105_xfer_u64(priv, SPI_WRITE, regs->ptpclkval, &ticks,
rc = sja1105_ptp_commit(ds, &cmd, SPI_WRITE);
return sja1105_ptp_commit(priv->ds, &ptp_data->cmd, SPI_WRITE);
rc = sja1105_xfer_u32(priv, SPI_WRITE, regs->ptpclkrate, &clkrate32,
rc = sja1105_xfer_u64(priv, SPI_WRITE, regs->ptppinst,
rc = sja1105_xfer_u32(priv, SPI_WRITE, regs->ptppindur,
rc = sja1105_ptp_commit(priv->ds, &cmd, SPI_WRITE);
if (rw == SPI_WRITE)
if (rw == SPI_WRITE) {
return sja1105_xfer_u32(priv, SPI_WRITE, regs->rgu, &cold_reset, NULL);
return sja1105_xfer_u32(priv, SPI_WRITE, regs->rgu, &cold_reset, NULL);
return sja1105_xfer_u32(priv, SPI_WRITE, regs->rgu, &switch_reset, NULL);
return sja1105_xfer_u32(priv, SPI_WRITE, regs->port_control,
rc = sja1105_xfer_buf(priv, SPI_WRITE, regs->config,
return sja1105_xfer_u32(priv, SPI_WRITE, regs->ptpclkcorp,
return sja1105_xfer_u64(priv, SPI_WRITE, regs->ptpschtm,
rc = sja1105_ptp_commit(ds, cmd, SPI_WRITE);
rc = sja1105_ptp_commit(ds, cmd, SPI_WRITE);
command = falcon_spi_munge_command(spi, SPI_WRITE, start + pos);