drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

420

uint32_t value[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

429

SMU7_Discrete_MCRegisterAddress address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1740

PP_ASSERT_WITH_CODE(i < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE,

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2567

PP_ASSERT_WITH_CODE((table->last <= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2599

PP_ASSERT_WITH_CODE((j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2615

PP_ASSERT_WITH_CODE((j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2631

PP_ASSERT_WITH_CODE((j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.h

50

uint32_t mc_data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.h

58

SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];

drivers/gpu/drm/radeon/ci_dpm.c

4296

if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)

drivers/gpu/drm/radeon/ci_dpm.c

4308

if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)

drivers/gpu/drm/radeon/ci_dpm.c

4321

if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)

drivers/gpu/drm/radeon/ci_dpm.c

4332

if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)

drivers/gpu/drm/radeon/ci_dpm.c

4345

if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)

drivers/gpu/drm/radeon/ci_dpm.c

4464

if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)

drivers/gpu/drm/radeon/ci_dpm.c

4501

if (table->last >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)

drivers/gpu/drm/radeon/ci_dpm.c

4644

if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)

drivers/gpu/drm/radeon/ci_dpm.h

79

u32 mc_data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];

drivers/gpu/drm/radeon/ci_dpm.h

87

SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];

drivers/gpu/drm/radeon/smu7_discrete.h

404

uint32_t value[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];

drivers/gpu/drm/radeon/smu7_discrete.h

412

SMU7_Discrete_MCRegisterAddress address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];