SMC_inw
(status) = SMC_inw(ioaddr, DATA_REG(lp)); \
(length) = SMC_inw(ioaddr, DATA_REG(lp)); \
*((u16 *)buf) = SMC_inw(ioaddr, reg);
: (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
: (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
: (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
: (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
: (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
__mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
: (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
#define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT)
#define SMC_GET_BASE(lp) SMC_inw(ioaddr, BASE_REG(lp))
#define SMC_GET_CONFIG(lp) SMC_inw(ioaddr, CONFIG_REG(lp))
#define SMC_GET_COUNTER(lp) SMC_inw(ioaddr, COUNTER_REG(lp))
#define SMC_GET_CTL(lp) SMC_inw(ioaddr, CTL_REG(lp))
#define SMC_GET_MII(lp) SMC_inw(ioaddr, MII_REG(lp))
#define SMC_GET_GP(lp) SMC_inw(ioaddr, GP_REG(lp))
#define SMC_GET_MIR(lp) SMC_inw(ioaddr, MIR_REG(lp))
#define SMC_GET_MMU_CMD(lp) SMC_inw(ioaddr, MMU_CMD_REG(lp))
#define SMC_GET_FIFO(lp) SMC_inw(ioaddr, FIFO_REG(lp))
#define SMC_GET_PTR(lp) SMC_inw(ioaddr, PTR_REG(lp))
#define SMC_GET_EPH_STATUS(lp) SMC_inw(ioaddr, EPH_STATUS_REG(lp))
#define SMC_GET_RCR(lp) SMC_inw(ioaddr, RCR_REG(lp))
#define SMC_GET_REV(lp) SMC_inw(ioaddr, REV_REG(lp))
#define SMC_GET_RPC(lp) SMC_inw(ioaddr, RPC_REG(lp))
#define SMC_GET_TCR(lp) SMC_inw(ioaddr, TCR_REG(lp))
__v = SMC_inw(ioaddr, ADDR0_REG(lp)); \
__v = SMC_inw(ioaddr, ADDR1_REG(lp)); \
__v = SMC_inw(ioaddr, ADDR2_REG(lp)); \