SOC_CORE_BASE_ADDRESS
addr = SOC_CORE_BASE_ADDRESS | CORE_CTRL_ADDRESS;
u32 address = SOC_CORE_BASE_ADDRESS + FW_RAM_CONFIG_ADDRESS;
#define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS
ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
addr = SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS;
ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS,
(void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
(void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS)
val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS)