arch/x86/events/intel/uncore_snb.c

144

#define SNB_UNC_RAW_EVENT_MASK (SNB_UNC_CTL_EV_SEL_MASK | \

arch/x86/events/intel/uncore_snb.c

150

#define NHM_UNC_RAW_EVENT_MASK (SNB_UNC_CTL_EV_SEL_MASK | \

arch/x86/events/intel/uncore_snb.c

1697

#define ADL_UNC_IMC_EVENT_MASK (SNB_UNC_CTL_EV_SEL_MASK | \

arch/x86/events/intel/uncore_snb.c

1793

#define LNL_UNC_RAW_EVENT_MASK (SNB_UNC_CTL_EV_SEL_MASK | \

arch/x86/events/intel/uncore_snb.c

211

#define ADL_UNC_RAW_EVENT_MASK (SNB_UNC_CTL_EV_SEL_MASK | \

arch/x86/events/intel/uncore_snb.c

503

.event_mask = SNB_UNC_CTL_EV_SEL_MASK,

arch/x86/events/intel/uncore_snb.c

647

.event_mask = SNB_UNC_CTL_EV_SEL_MASK,

arch/x86/events/intel/uncore_snb.c

738

.event_mask = SNB_UNC_CTL_EV_SEL_MASK,

arch/x86/events/intel/uncore_snb.c

753

.event_mask = SNB_UNC_CTL_EV_SEL_MASK,