SMU_SCLK_DPM_STATE_0_CNTL_0
value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);
WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);
value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);
WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);
value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);
WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);
value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);
WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);
#define TRINITY_SIZEOF_DPM_STATE_TABLE (SMU_SCLK_DPM_STATE_1_CNTL_0 - SMU_SCLK_DPM_STATE_0_CNTL_0)