SMU_CAP
if (smu_v13_0_6_cap_supported(smu, SMU_CAP(RAS_EEPROM)))
if (smu_v13_0_6_cap_supported(smu, SMU_CAP(BOARD_VOLTAGE))) {
if (smu_v13_0_6_cap_supported(smu, SMU_CAP(PLDM_VERSION)) &&
if (smu_v13_0_6_cap_supported(smu, SMU_CAP(NPM_METRICS)))
if (smu_v13_0_6_cap_supported(smu, SMU_CAP(FAST_PPT)) &&
smu_v13_0_6_cap_supported(smu, SMU_CAP(TEMP_METRICS)))
return smu_v13_0_6_cap_supported(smu, SMU_CAP(TEMP_METRICS));
if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(SYSTEM_POWER_METRICS)))
if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(NPM_METRICS)))
if (smu_v13_0_6_cap_supported(smu, SMU_CAP(HST_LIMIT_METRICS))) {
SMU_CAP(HST_LIMIT_METRICS))) {
if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(DPM_POLICY))) {
smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS)))
if (smu_v13_0_6_cap_supported(smu, SMU_CAP(DPM))) {
if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(SET_UCLK_MAX)))
if (smu_v13_0_6_cap_supported(smu, SMU_CAP(BOARD_VOLTAGE))) {
if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(FAST_PPT)))
if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(FAST_PPT)))
if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(MCA_DEBUG_MODE)))
SMU_CAP(SET_UCLK_MAX)))
if (ret == -EIO && !smu_v13_0_6_cap_supported(smu, SMU_CAP(DPM))) {
smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS)))
per_inst = smu_v13_0_6_cap_supported(smu, SMU_CAP(PER_INST_METRICS));
smu, SMU_CAP(HST_LIMIT_METRICS))) {
smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS))) {
if (smu_v13_0_6_cap_supported(smu, SMU_CAP(PCIE_METRICS))) {
if (smu_v13_0_6_cap_supported(smu, SMU_CAP(OTHER_END_METRICS)))
per_inst = smu_v13_0_6_cap_supported(smu, SMU_CAP(PER_INST_METRICS));
smu, SMU_CAP(HST_LIMIT_METRICS))) {
enum smu_v13_0_6_caps default_cap_list[] = { SMU_CAP(DPM),
if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(CTF_LIMIT)))
SMU_CAP(SET_UCLK_MAX),
SMU_CAP(DPM_POLICY),
SMU_CAP(PCIE_METRICS),
SMU_CAP(CTF_LIMIT),
SMU_CAP(MCA_DEBUG_MODE),
SMU_CAP(RMA_MSG),
SMU_CAP(ACA_SYND) };
if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(RMA_MSG)))
smu_v13_0_6_cap_set(smu, SMU_CAP(OTHER_END_METRICS));
if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(SDMA_RESET))) {
smu_v13_0_6_cap_set(smu, SMU_CAP(PER_INST_METRICS));
return smu_v13_0_6_cap_supported(smu, SMU_CAP(VCN_RESET));
smu_v13_0_6_cap_set(smu, SMU_CAP(SDMA_RESET));
smu_v13_0_6_cap_set(smu, SMU_CAP(VCN_RESET));
smu_v13_0_6_cap_set(smu, SMU_CAP(STATIC_METRICS));
smu_v13_0_6_cap_set(smu, SMU_CAP(BOARD_VOLTAGE));
smu_v13_0_6_cap_set(smu, SMU_CAP(PLDM_VERSION));
enum smu_v13_0_6_caps default_cap_list[] = { SMU_CAP(DPM),
SMU_CAP(PCIE_METRICS),
SMU_CAP(CTF_LIMIT),
SMU_CAP(MCA_DEBUG_MODE),
SMU_CAP(RMA_MSG),
SMU_CAP(ACA_SYND),
SMU_CAP(OTHER_END_METRICS),
SMU_CAP(PER_INST_METRICS) };
smu_v13_0_6_cap_clear(smu, SMU_CAP(DPM));
smu_v13_0_6_cap_set(smu, SMU_CAP(SDMA_RESET));
smu_v13_0_6_cap_set(smu, SMU_CAP(STATIC_METRICS));
smu_v13_0_6_cap_set(smu, SMU_CAP(HST_LIMIT_METRICS));
if (smu_v13_0_6_cap_supported(smu, SMU_CAP(ACA_SYND))) {
smu_v13_0_6_cap_set(smu, SMU_CAP(BOARD_VOLTAGE));
smu_v13_0_6_cap_set(smu, SMU_CAP(PLDM_VERSION));
smu_v13_0_6_cap_set(smu, SMU_CAP(VCN_RESET));
smu_v13_0_6_cap_set(smu, SMU_CAP(FAST_PPT));
smu_v13_0_6_cap_set(smu, SMU_CAP(SYSTEM_POWER_METRICS));
smu_v13_0_6_cap_set(smu, SMU_CAP(TEMP_METRICS));
smu_v13_0_6_cap_set(smu, SMU_CAP(NPM_METRICS));
smu_v13_0_6_cap_set(smu, SMU_CAP(TEMP_METRICS));
if (smu_v13_0_6_cap_supported(smu, SMU_CAP(ACA_SYND)))
enum smu_v13_0_6_caps default_cap_list[] = { SMU_CAP(DPM),
SMU_CAP(SET_UCLK_MAX),
SMU_CAP(DPM_POLICY),
smu_v13_0_6_cap_set(smu, SMU_CAP(RAS_EEPROM));
SMU_CAP(PCIE_METRICS),
SMU_CAP(CTF_LIMIT),
SMU_CAP(MCA_DEBUG_MODE),
SMU_CAP(RMA_MSG),
SMU_CAP(ACA_SYND) };
smu_v13_0_6_cap_clear(smu, SMU_CAP(DPM));
smu_v13_0_6_cap_clear(smu, SMU_CAP(CTF_LIMIT));
smu_v13_0_6_cap_clear(smu, SMU_CAP(PCIE_METRICS));
smu_v13_0_6_cap_clear(smu, SMU_CAP(DPM_POLICY));
smu_v13_0_6_cap_clear(smu, SMU_CAP(RMA_MSG));
smu_v13_0_6_cap_clear(smu, SMU_CAP(ACA_SYND));
smu_v13_0_6_cap_set(smu, SMU_CAP(PER_INST_METRICS));
smu_v13_0_6_cap_set(smu, SMU_CAP(OTHER_END_METRICS));
smu_v13_0_6_cap_clear(smu, SMU_CAP(DPM_POLICY));
smu_v13_0_6_cap_clear(smu, SMU_CAP(SET_UCLK_MAX));
smu_v13_0_6_cap_clear(smu, SMU_CAP(PCIE_METRICS));
smu_v13_0_6_cap_clear(smu, SMU_CAP(MCA_DEBUG_MODE));
smu_v13_0_6_cap_set(smu, SMU_CAP(PER_INST_METRICS));
smu_v13_0_6_cap_clear(smu, SMU_CAP(RMA_MSG));
smu_v13_0_6_cap_clear(smu, SMU_CAP(ACA_SYND));
smu_v13_0_6_cap_set(smu, SMU_CAP(HST_LIMIT_METRICS));
SMU_CAP(STATIC_METRICS));
SMU_CAP(BOARD_VOLTAGE));
smu_v13_0_6_cap_set(smu, SMU_CAP(PLDM_VERSION));
SMU_CAP(STATIC_METRICS));
SMU_CAP(BOARD_VOLTAGE));
smu_v13_0_6_cap_set(smu, SMU_CAP(PLDM_VERSION));
smu_v13_0_6_cap_set(smu, SMU_CAP(SDMA_RESET));
smu_v13_0_6_cap_set(smu, SMU_CAP(VCN_RESET));
if (smu_v13_0_6_cap_supported(smu, SMU_CAP(PLDM_VERSION)) &&
if (smu_v13_0_6_cap_supported(smu, SMU_CAP(FAST_PPT)) &&
smu_v13_0_6_cap_clear(smu, SMU_CAP(FAST_PPT));
smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS))) {
if (smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS))) {