drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

433

typedef struct SMU7_Discrete_MCRegisters SMU7_Discrete_MCRegisters;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1724

SMU7_Discrete_MCRegisters *mc_reg_table)

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1789

SMU7_Discrete_MCRegisters *mc_regs)

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1821

memset(&smu_data->mc_regs, 0, sizeof(SMU7_Discrete_MCRegisters));

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1828

address = smu_data->mc_reg_table_start + (uint32_t)offsetof(SMU7_Discrete_MCRegisters, data[0]);

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1841

memset(&smu_data->mc_regs, 0x00, sizeof(SMU7_Discrete_MCRegisters));

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1851

(uint8_t *)&smu_data->mc_regs, sizeof(SMU7_Discrete_MCRegisters), SMC_RAM_END);

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.h

71

SMU7_Discrete_MCRegisters mc_regs;

drivers/gpu/drm/radeon/ci_dpm.c

4634

SMU7_Discrete_MCRegisters *mc_reg_table)

drivers/gpu/drm/radeon/ci_dpm.c

4689

SMU7_Discrete_MCRegisters *mc_reg_table)

drivers/gpu/drm/radeon/ci_dpm.c

4705

memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));

drivers/gpu/drm/radeon/ci_dpm.c

4715

sizeof(SMU7_Discrete_MCRegisters),

drivers/gpu/drm/radeon/ci_dpm.c

4726

memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));

drivers/gpu/drm/radeon/ci_dpm.c

4732

offsetof(SMU7_Discrete_MCRegisters, data[0]),

drivers/gpu/drm/radeon/ci_dpm.h

223

SMU7_Discrete_MCRegisters smc_mc_reg_table;

drivers/gpu/drm/radeon/smu7_discrete.h

416

typedef struct SMU7_Discrete_MCRegisters SMU7_Discrete_MCRegisters;