drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

357

typedef struct SMU73_Discrete_DpmTable SMU73_Discrete_DpmTable;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1011

offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1227

offsetof(SMU73_Discrete_DpmTable, MemoryLevel);

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1297

SMU73_Discrete_DpmTable *table)

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1419

SMU73_Discrete_DpmTable *table)

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1458

SMU73_Discrete_DpmTable *table)

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1554

struct SMU73_Discrete_DpmTable *table)

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1601

struct SMU73_Discrete_DpmTable *table)

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1818

struct SMU73_Discrete_DpmTable *table)

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1925

struct SMU73_Discrete_DpmTable *table = &(smu_data->smc_state_table);

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2106

offsetof(SMU73_Discrete_DpmTable, SystemFlags),

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2108

sizeof(SMU73_Discrete_DpmTable) - 3 * sizeof(SMU73_PIDController),

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2280

offsetof(SMU73_Discrete_DpmTable,

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2327

return offsetof(SMU73_Discrete_DpmTable, UvdBootLevel);

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2329

return offsetof(SMU73_Discrete_DpmTable, VceBootLevel);

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2331

return offsetof(SMU73_Discrete_DpmTable, LowSclkInterruptThreshold);

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2376

mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU73_Discrete_DpmTable,

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2413

offsetof(SMU73_Discrete_DpmTable, VceBootLevel);

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

242

offsetof(SMU73_Discrete_DpmTable, VRConfig);

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

250

level_addr = table_start + offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2557

offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2560

offsetof(SMU73_Discrete_DpmTable, MemoryLevel);

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

490

SMU73_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table);

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

755

struct SMU73_Discrete_DpmTable *table)

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

783

struct SMU73_Discrete_DpmTable *table)

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

821

struct SMU73_Discrete_DpmTable *table)

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

827

struct SMU73_Discrete_DpmTable *table)

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.h

42

struct SMU73_Discrete_DpmTable smc_state_table;