drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

265

SMU72_Discrete_GraphicsLevel GraphicsLevel[SMU72_MAX_LEVELS_GRAPHICS];

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

72

typedef struct SMU72_Discrete_GraphicsLevel SMU72_Discrete_GraphicsLevel;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

3153

struct SMU72_Discrete_GraphicsLevel *levels =

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

3178

clk_activity_offset = array + (sizeof(SMU72_Discrete_GraphicsLevel) * i)

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

3179

+ offsetof(SMU72_Discrete_GraphicsLevel, ActivityLevel);

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

3190

up_hyst_offset = array + (sizeof(SMU72_Discrete_GraphicsLevel) * i)

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

3191

+ offsetof(SMU72_Discrete_GraphicsLevel, UpHyst);

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

3192

down_hyst_offset = array + (sizeof(SMU72_Discrete_GraphicsLevel) * i)

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

3193

+ offsetof(SMU72_Discrete_GraphicsLevel, DownHyst);

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

539

uint32_t engine_clock, SMU72_Discrete_GraphicsLevel *sclk)

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

618

SMU72_Discrete_GraphicsLevel *graphic_level)

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

697

uint32_t level_array_size = sizeof(SMU72_Discrete_GraphicsLevel) *

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

700

SMU72_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel;