drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

360

uint32_t value[SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE];

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

369

SMU71_Discrete_MCRegisterAddress address[SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE];

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1697

PP_ASSERT_WITH_CODE(i < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE,

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2486

PP_ASSERT_WITH_CODE((table->last <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2518

PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2534

PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2551

PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.h

49

uint32_t mc_data[SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE];

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.h

57

SMU71_Discrete_MCRegisterAddress mc_reg_address[SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE];