drivers/gpu/drm/i915/i915_cmd_parser.c

221

CMD( MI_NOOP, SMI, F, 1, S ),

drivers/gpu/drm/i915/i915_cmd_parser.c

222

CMD( MI_USER_INTERRUPT, SMI, F, 1, R ),

drivers/gpu/drm/i915/i915_cmd_parser.c

223

CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, R ),

drivers/gpu/drm/i915/i915_cmd_parser.c

224

CMD( MI_ARB_CHECK, SMI, F, 1, S ),

drivers/gpu/drm/i915/i915_cmd_parser.c

225

CMD( MI_REPORT_HEAD, SMI, F, 1, S ),

drivers/gpu/drm/i915/i915_cmd_parser.c

226

CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ),

drivers/gpu/drm/i915/i915_cmd_parser.c

227

CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, R ),

drivers/gpu/drm/i915/i915_cmd_parser.c

228

CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ),

drivers/gpu/drm/i915/i915_cmd_parser.c

229

CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,

drivers/gpu/drm/i915/i915_cmd_parser.c

231

CMD( MI_STORE_REGISTER_MEM, SMI, F, 3, W | B,

drivers/gpu/drm/i915/i915_cmd_parser.c

238

CMD( MI_LOAD_REGISTER_MEM, SMI, F, 3, W | B,

drivers/gpu/drm/i915/i915_cmd_parser.c

250

CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ),

drivers/gpu/drm/i915/i915_cmd_parser.c

254

CMD( MI_FLUSH, SMI, F, 1, S ),

drivers/gpu/drm/i915/i915_cmd_parser.c

255

CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),

drivers/gpu/drm/i915/i915_cmd_parser.c

256

CMD( MI_PREDICATE, SMI, F, 1, S ),

drivers/gpu/drm/i915/i915_cmd_parser.c

257

CMD( MI_TOPOLOGY_FILTER, SMI, F, 1, S ),

drivers/gpu/drm/i915/i915_cmd_parser.c

258

CMD( MI_SET_APPID, SMI, F, 1, S ),

drivers/gpu/drm/i915/i915_cmd_parser.c

259

CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ),

drivers/gpu/drm/i915/i915_cmd_parser.c

260

CMD( MI_SET_CONTEXT, SMI, !F, 0xFF, R ),

drivers/gpu/drm/i915/i915_cmd_parser.c

261

CMD( MI_URB_CLEAR, SMI, !F, 0xFF, S ),

drivers/gpu/drm/i915/i915_cmd_parser.c

262

CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3F, B,

drivers/gpu/drm/i915/i915_cmd_parser.c

268

CMD( MI_UPDATE_GTT, SMI, !F, 0xFF, R ),

drivers/gpu/drm/i915/i915_cmd_parser.c

269

CMD( MI_CLFLUSH, SMI, !F, 0x3FF, B,

drivers/gpu/drm/i915/i915_cmd_parser.c

275

CMD( MI_REPORT_PERF_COUNT, SMI, !F, 0x3F, B,

drivers/gpu/drm/i915/i915_cmd_parser.c

281

CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,

drivers/gpu/drm/i915/i915_cmd_parser.c

315

CMD( MI_SET_PREDICATE, SMI, F, 1, S ),

drivers/gpu/drm/i915/i915_cmd_parser.c

316

CMD( MI_RS_CONTROL, SMI, F, 1, S ),

drivers/gpu/drm/i915/i915_cmd_parser.c

317

CMD( MI_URB_ATOMIC_ALLOC, SMI, F, 1, S ),

drivers/gpu/drm/i915/i915_cmd_parser.c

318

CMD( MI_SET_APPID, SMI, F, 1, S ),

drivers/gpu/drm/i915/i915_cmd_parser.c

319

CMD( MI_RS_CONTEXT, SMI, F, 1, S ),

drivers/gpu/drm/i915/i915_cmd_parser.c

320

CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, R ),

drivers/gpu/drm/i915/i915_cmd_parser.c

321

CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ),

drivers/gpu/drm/i915/i915_cmd_parser.c

322

CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, W,

drivers/gpu/drm/i915/i915_cmd_parser.c

324

CMD( MI_RS_STORE_DATA_IMM, SMI, !F, 0xFF, S ),

drivers/gpu/drm/i915/i915_cmd_parser.c

325

CMD( MI_LOAD_URB_MEM, SMI, !F, 0xFF, S ),

drivers/gpu/drm/i915/i915_cmd_parser.c

326

CMD( MI_STORE_URB_MEM, SMI, !F, 0xFF, S ),

drivers/gpu/drm/i915/i915_cmd_parser.c

338

CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),

drivers/gpu/drm/i915/i915_cmd_parser.c

339

CMD( MI_SET_APPID, SMI, F, 1, S ),

drivers/gpu/drm/i915/i915_cmd_parser.c

340

CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B,

drivers/gpu/drm/i915/i915_cmd_parser.c

346

CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),

drivers/gpu/drm/i915/i915_cmd_parser.c

347

CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,

drivers/gpu/drm/i915/i915_cmd_parser.c

367

CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,

drivers/gpu/drm/i915/i915_cmd_parser.c

382

CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),

drivers/gpu/drm/i915/i915_cmd_parser.c

383

CMD( MI_SET_APPID, SMI, F, 1, S ),

drivers/gpu/drm/i915/i915_cmd_parser.c

384

CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B,

drivers/gpu/drm/i915/i915_cmd_parser.c

390

CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),

drivers/gpu/drm/i915/i915_cmd_parser.c

391

CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,

drivers/gpu/drm/i915/i915_cmd_parser.c

411

CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,

drivers/gpu/drm/i915/i915_cmd_parser.c

420

CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ),

drivers/gpu/drm/i915/i915_cmd_parser.c

421

CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, B,

drivers/gpu/drm/i915/i915_cmd_parser.c

427

CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),

drivers/gpu/drm/i915/i915_cmd_parser.c

428

CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,

drivers/gpu/drm/i915/i915_cmd_parser.c

453

CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, R ),

drivers/gpu/drm/i915/i915_cmd_parser.c

454

CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ),

drivers/gpu/drm/i915/i915_cmd_parser.c

475

CMD( MI_NOOP, SMI, F, 1, S ),

drivers/gpu/drm/i915/i915_cmd_parser.c

476

CMD( MI_USER_INTERRUPT, SMI, F, 1, S ),

drivers/gpu/drm/i915/i915_cmd_parser.c

477

CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, S ),

drivers/gpu/drm/i915/i915_cmd_parser.c

478

CMD( MI_FLUSH, SMI, F, 1, S ),

drivers/gpu/drm/i915/i915_cmd_parser.c

479

CMD( MI_ARB_CHECK, SMI, F, 1, S ),

drivers/gpu/drm/i915/i915_cmd_parser.c

480

CMD( MI_REPORT_HEAD, SMI, F, 1, S ),

drivers/gpu/drm/i915/i915_cmd_parser.c

481

CMD( MI_ARB_ON_OFF, SMI, F, 1, S ),

drivers/gpu/drm/i915/i915_cmd_parser.c

482

CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ),

drivers/gpu/drm/i915/i915_cmd_parser.c

483

CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, S ),

drivers/gpu/drm/i915/i915_cmd_parser.c

484

CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, S ),

drivers/gpu/drm/i915/i915_cmd_parser.c

485

CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, S ),

drivers/gpu/drm/i915/i915_cmd_parser.c

486

CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,

drivers/gpu/drm/i915/i915_cmd_parser.c

488

CMD( MI_UPDATE_GTT, SMI, !F, 0x3FF, S ),

drivers/gpu/drm/i915/i915_cmd_parser.c

489

CMD( MI_STORE_REGISTER_MEM_GEN8, SMI, F, 4, W,

drivers/gpu/drm/i915/i915_cmd_parser.c

491

CMD( MI_FLUSH_DW, SMI, !F, 0x3F, S ),

drivers/gpu/drm/i915/i915_cmd_parser.c

492

CMD( MI_LOAD_REGISTER_MEM_GEN8, SMI, F, 4, W,

drivers/gpu/drm/i915/i915_cmd_parser.c

494

CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, W,

drivers/gpu/drm/i915/i915_cmd_parser.c

501

#define MI_BB_START_OPERAND_MASK GENMASK(SMI-1, 0)

drivers/gpu/drm/i915/i915_cmd_parser.c

503

CMD( MI_BATCH_BUFFER_START_GEN8, SMI, !F, 0xFF, B,

drivers/gpu/drm/i915/i915_cmd_parser.c

512

CMD(MI_NOOP, SMI, F, 1, S);

drivers/infiniband/core/cma_trace.h

142

ib_qp_type(SMI) \

drivers/net/ethernet/amd/xgbe/xgbe-drv.c

488

if (XGMAC_GET_BITS(mac_isr, MAC_ISR, SMI)) {

drivers/net/ethernet/marvell/pxa168_eth.c

1291

for (i = 0; rdl(pep, SMI) & SMI_BUSY; i++) {

drivers/net/ethernet/marvell/pxa168_eth.c

1310

wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) | SMI_OP_R);

drivers/net/ethernet/marvell/pxa168_eth.c

1312

for (i = 0; !((val = rdl(pep, SMI)) & SMI_R_VALID); i++) {

drivers/net/ethernet/marvell/pxa168_eth.c

1334

wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) |

drivers/pmdomain/mediatek/mt8183-pm-domains.h

120

BUS_PROT_WR(SMI,

drivers/pmdomain/mediatek/mt8183-pm-domains.h

151

BUS_PROT_WR(SMI,

drivers/pmdomain/mediatek/mt8183-pm-domains.h

177

BUS_PROT_WR(SMI,

drivers/pmdomain/mediatek/mt8183-pm-domains.h

193

BUS_PROT_WR(SMI,

drivers/pmdomain/mediatek/mt8183-pm-domains.h

209

BUS_PROT_WR(SMI,

drivers/pmdomain/mediatek/mt8183-pm-domains.h

240

BUS_PROT_WR(SMI,

drivers/pmdomain/mediatek/mt8365-pm-domains.h

26

BUS_PROT_WR(SMI, BIT(port), \