SMC_SYSCON_RESET_CNTL
u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL) |
WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 0);
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 1);
SMC_SYSCON_RESET_CNTL,
SMC_SYSCON_RESET_CNTL, rst_reg, 1);
SMC_SYSCON_RESET_CNTL, rst_reg, 0);
SMC_SYSCON_RESET_CNTL, rst_reg, 1);
SMC_SYSCON_RESET_CNTL, rst_reg, 0);
SMC_SYSCON_RESET_CNTL, rst_reg, 0);
SMC_SYSCON_RESET_CNTL,
SMC_SYSCON_RESET_CNTL, rst_reg, 1);
SMC_SYSCON_RESET_CNTL, rst_reg, 0);
SMC_SYSCON_RESET_CNTL, rst_reg, 1);
SMC_SYSCON_RESET_CNTL, rst_reg, 0);
SMC_SYSCON_RESET_CNTL,
SMC_SYSCON_RESET_CNTL, rst_reg, 0);
SMC_SYSCON_RESET_CNTL, rst_reg, 1);
SMC_SYSCON_RESET_CNTL, rst_reg, 0);
SMC_SYSCON_RESET_CNTL, rst_reg, 1);
SMC_SYSCON_RESET_CNTL, rst_reg, 0);
SMC_SYSCON_RESET_CNTL, rst_reg, 1);
SMC_SYSCON_RESET_CNTL, rst_reg, 0);
SMC_SYSCON_RESET_CNTL, rst_reg, 1);
SMC_SYSCON_RESET_CNTL, rst_reg, 0);
SMC_SYSCON_RESET_CNTL,
SMC_SYSCON_RESET_CNTL, rst_reg, 0);
u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL);