drivers/gpu/drm/amd/amdgpu/cik.c

1941

if ((0 == REG_GET_FIELD(clock_cntl, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) &&

drivers/gpu/drm/amd/amdgpu/vi.c

1420

if ((0 == REG_GET_FIELD(clock_cntl, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) &&

drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c

149

u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c

156

WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);

drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c

162

u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c

222

tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

189

CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable))

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1901

PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2363

PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 1);

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2952

SMC_SYSCON_CLOCK_CNTL_0,

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

119

SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

185

SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

128

SMC_SYSCON_CLOCK_CNTL_0,

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

135

SMC_SYSCON_CLOCK_CNTL_0,

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

219

SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

279

SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);

drivers/gpu/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

126

return ((0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable))

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

115

SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

181

SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

119

SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

179

SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);

drivers/gpu/drm/radeon/ci_smc.c

139

u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

drivers/gpu/drm/radeon/ci_smc.c

143

WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);

drivers/gpu/drm/radeon/ci_smc.c

148

u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

drivers/gpu/drm/radeon/ci_smc.c

152

WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);

drivers/gpu/drm/radeon/ci_smc.c

157

u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

drivers/gpu/drm/radeon/ci_smc.c

176

tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

drivers/gpu/drm/radeon/si_smc.c

145

u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

drivers/gpu/drm/radeon/si_smc.c

149

WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);

drivers/gpu/drm/radeon/si_smc.c

154

u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

drivers/gpu/drm/radeon/si_smc.c

158

WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);

drivers/gpu/drm/radeon/si_smc.c

164

u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

drivers/gpu/drm/radeon/si_smc.c

202

tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);