SMC_REG
#define TCR_REG(lp) SMC_REG(lp, 0x0000, 0)
#define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0)
#define RCR_REG(lp) SMC_REG(lp, 0x0004, 0)
#define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0)
#define MIR_REG(lp) SMC_REG(lp, 0x0008, 0)
#define RPC_REG(lp) SMC_REG(lp, 0x000A, 0)
#define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1)
#define BASE_REG(lp) SMC_REG(lp, 0x0002, 1)
#define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1)
#define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1)
#define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1)
#define GP_REG(lp) SMC_REG(lp, 0x000A, 1)
#define CTL_REG(lp) SMC_REG(lp, 0x000C, 1)
#define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2)
#define PN_REG(lp) SMC_REG(lp, 0x0002, 2)
#define AR_REG(lp) SMC_REG(lp, 0x0003, 2)
#define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
#define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2)
#define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
#define PTR_REG(lp) SMC_REG(lp, 0x0006, 2)
#define DATA_REG(lp) SMC_REG(lp, 0x0008, 2)
#define INT_REG(lp) SMC_REG(lp, 0x000C, 2)
#define IM_REG(lp) SMC_REG(lp, 0x000D, 2)
#define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3)
#define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3)
#define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3)
#define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3)
#define MII_REG(lp) SMC_REG(lp, 0x0008, 3)
#define REV_REG(lp) SMC_REG(lp, 0x000A, 3)
#define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3)
#define EXT_REG(lp) SMC_REG(lp, 0x0000, 7)
SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \
SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 1)); \
SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \
SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \