BCS0
[I915_EXEC_BLT] = BCS0,
case BCS0:
ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS)
if (i915_ggtt_require_binder(engine->i915) && engine->id == BCS0) {
[BCS0] = MSG_IDLE_BCS,
[BCS0] = GEN11_GRDOM_BLT,
[BCS0] = GEN6_GRDOM_BLT,
[BCS0] = {
[COPY_ENGINE_CLASS] = { BCS0, 1 },
[BCS0] = GEN8_BCS_IRQ_SHIFT,
ce = gt->engine[BCS0]->bind_context;
struct intel_engine_cs *engine = gt->engine[BCS0];
struct intel_engine_cs *engine = gt->engine[BCS0];
[BCS0] = __GEN9_BCS0_MOCS0,
case BCS0:
if (s->engine->id == BCS0 &&
[BCS0] = {
#define R_BCS BIT(BCS0)
[BCS0] = {
[BCS0] = BCS_AS_CONTEXT_SWITCH,
id = BCS0;
engine_mask |= BIT(BCS0);
{BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
{BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
{BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
{BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
{BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */
[BCS0] = 0xcc00,
[BCS0] = 0x426c,
[BCS0] = 0xcc00,
{BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
{BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
{BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
{BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
{BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */
} else if (workload->engine->id == BCS0)
case BCS0:
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
BIT(RCS0) | BIT(BCS0) | \
.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),