Symbol: SMBUS_MAST_CORE_ADDR_BASE
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
100
#define SMB_CORE_BUS_CLK_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x2C)
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
125
#define SMB_CORE_CLK_SYNC_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x3C)
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
136
#define SMB_CORE_DATA_TIMING_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x40)
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
186
#define SMB_CORE_TO_SCALING_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x44)
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
233
#define I2C_SCL_PAD_CTRL_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x100)
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
234
#define I2C_SDA_PAD_CTRL_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x101)
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
242
#define SMBUS_CONTROL_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x200)
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
252
#define SMBUS_STATUS_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x204)
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
26
#define SMB_CORE_CTRL_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x00)
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
260
#define SMBUS_INTR_STAT_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x208)
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
267
#define SMBUS_INTR_MSK_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x20C)
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
278
#define SMBUS_MCU_COUNTER_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x214)
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
280
#define SMBALERT_MST_PAD_CTRL_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x230)
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
284
#define SMBUS_GEN_INT_STAT_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x23C)
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
286
#define SMBUS_GEN_INT_MASK_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x240)
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
300
#define SMBUS_RESET_REG (SMBUS_MAST_CORE_ADDR_BASE + 0x248)
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
304
#define SMBUS_MST_BUF (SMBUS_MAST_CORE_ADDR_BASE + 0x280)
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
316
#define SMB_GPR_REG (SMBUS_MAST_CORE_ADDR_BASE + 0x1000 + 0x0c00 + \
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
32
#define SMB_CORE_CMD_REG_OFF3 (SMBUS_MAST_CORE_ADDR_BASE + 0x0F)
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
320
#define SMB_GPR_LOCK_REG (SMBUS_MAST_CORE_ADDR_BASE + 0x1000 + 0x0000 + \
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
33
#define SMB_CORE_CMD_REG_OFF2 (SMBUS_MAST_CORE_ADDR_BASE + 0x0E)
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
34
#define SMB_CORE_CMD_REG_OFF1 (SMBUS_MAST_CORE_ADDR_BASE + 0x0D)
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
40
#define SMB_CORE_CMD_REG_OFF0 (SMBUS_MAST_CORE_ADDR_BASE + 0x0C)
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
45
#define SMB_CORE_SR_HOLD_TIME_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x18)
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
55
#define SMB_CORE_COMPLETION_REG_OFF3 (SMBUS_MAST_CORE_ADDR_BASE + 0x23)
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
61
#define SMB_CORE_IDLE_SCALING_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x24)
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
87
#define SMB_CORE_CONFIG_REG3 (SMBUS_MAST_CORE_ADDR_BASE + 0x2B)
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
92
#define SMB_CORE_CONFIG_REG2 (SMBUS_MAST_CORE_ADDR_BASE + 0x2A)
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
93
#define SMB_CORE_CONFIG_REG1 (SMBUS_MAST_CORE_ADDR_BASE + 0x29)