SG2042_GATE_HWS
SG2042_GATE_HWS(GATE_CLK_DDR01, "clk_gate_ddr01", clk_mux_ddr01,
SG2042_GATE_HWS(GATE_CLK_DDR23, "clk_gate_ddr23", clk_mux_ddr23,
SG2042_GATE_HWS(GATE_CLK_RP_CPU_NORMAL,
SG2042_GATE_HWS(GATE_CLK_AXI_DDR, "clk_gate_axi_ddr", clk_mux_axi_ddr,
SG2042_GATE_HWS(GATE_CLK_HSDMA, "clk_gate_hsdma", clk_gate_top_rp_cmn_div2,
SG2042_GATE_HWS(GATE_CLK_AXI_PCIE0,
SG2042_GATE_HWS(GATE_CLK_AXI_PCIE1,