SG2042_DIV_HWS
SG2042_DIV_HWS(DIV_CLK_MPLL_RP_CPU_NORMAL_0,
SG2042_DIV_HWS(DIV_CLK_FPLL_RP_CPU_NORMAL_1,
SG2042_DIV_HWS(DIV_CLK_MPLL_AXI_DDR_0,
SG2042_DIV_HWS(DIV_CLK_FPLL_AXI_DDR_1,
SG2042_DIV_HWS(DIV_CLK_FPLL_TOP_RP_CMN_DIV2,