drivers/gpu/drm/i915/i915_hwmon.c

428

SF_POWER);

drivers/gpu/drm/i915/i915_hwmon.c

433

min = mul_u64_u32_shr(min, SF_POWER, hwmon->scl_shift_power);

drivers/gpu/drm/i915/i915_hwmon.c

435

max = mul_u64_u32_shr(max, SF_POWER, hwmon->scl_shift_power);

drivers/gpu/drm/i915/i915_hwmon.c

488

nval = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_power, SF_POWER);

drivers/gpu/drm/i915/i915_hwmon.c

514

SF_POWER);

drivers/gpu/drm/i915/i915_hwmon.c

523

SF_POWER, POWER_SETUP_I1_SHIFT);

drivers/gpu/drm/i915/i915_hwmon.c

539

uval = DIV_ROUND_CLOSEST_ULL(val << POWER_SETUP_I1_SHIFT, SF_POWER);

drivers/gpu/drm/xe/xe_hwmon.c

1157

return xe_hwmon_power_curr_crit_read(hwmon, channel, val, SF_POWER);

drivers/gpu/drm/xe/xe_hwmon.c

1171

return xe_hwmon_power_curr_crit_write(hwmon, channel, val, SF_POWER);

drivers/gpu/drm/xe/xe_hwmon.c

367

*value = mul_u32_u32(reg_val, SF_POWER) >> hwmon->scl_shift_power;

drivers/gpu/drm/xe/xe_hwmon.c

376

min = mul_u64_u32_shr(min, SF_POWER, hwmon->scl_shift_power);

drivers/gpu/drm/xe/xe_hwmon.c

377

max = mul_u64_u32_shr(max, SF_POWER, hwmon->scl_shift_power);

drivers/gpu/drm/xe/xe_hwmon.c

422

max_supp_power_limit = ((PWR_LIM_VAL) >> hwmon->scl_shift_power) * SF_POWER;

drivers/gpu/drm/xe/xe_hwmon.c

431

reg_val = DIV_ROUND_CLOSEST_ULL((u64)value << hwmon->scl_shift_power, SF_POWER);

drivers/gpu/drm/xe/xe_hwmon.c

481

*value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon->scl_shift_power);