drivers/gpu/drm/i915/gvt/interrupt.c

589

SET_BIT_INFO(irq, 0, RCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT0);

drivers/gpu/drm/i915/gvt/interrupt.c

590

SET_BIT_INFO(irq, 4, RCS_PIPE_CONTROL, INTEL_GVT_IRQ_INFO_GT0);

drivers/gpu/drm/i915/gvt/interrupt.c

591

SET_BIT_INFO(irq, 8, RCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT0);

drivers/gpu/drm/i915/gvt/interrupt.c

593

SET_BIT_INFO(irq, 16, BCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT0);

drivers/gpu/drm/i915/gvt/interrupt.c

594

SET_BIT_INFO(irq, 20, BCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT0);

drivers/gpu/drm/i915/gvt/interrupt.c

595

SET_BIT_INFO(irq, 24, BCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT0);

drivers/gpu/drm/i915/gvt/interrupt.c

598

SET_BIT_INFO(irq, 0, VCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT1);

drivers/gpu/drm/i915/gvt/interrupt.c

599

SET_BIT_INFO(irq, 4, VCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT1);

drivers/gpu/drm/i915/gvt/interrupt.c

600

SET_BIT_INFO(irq, 8, VCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT1);

drivers/gpu/drm/i915/gvt/interrupt.c

603

SET_BIT_INFO(irq, 16, VCS2_MI_USER_INTERRUPT,

drivers/gpu/drm/i915/gvt/interrupt.c

605

SET_BIT_INFO(irq, 20, VCS2_MI_FLUSH_DW,

drivers/gpu/drm/i915/gvt/interrupt.c

607

SET_BIT_INFO(irq, 24, VCS2_AS_CONTEXT_SWITCH,

drivers/gpu/drm/i915/gvt/interrupt.c

612

SET_BIT_INFO(irq, 0, VECS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT3);

drivers/gpu/drm/i915/gvt/interrupt.c

613

SET_BIT_INFO(irq, 4, VECS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT3);

drivers/gpu/drm/i915/gvt/interrupt.c

614

SET_BIT_INFO(irq, 8, VECS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT3);

drivers/gpu/drm/i915/gvt/interrupt.c

616

SET_BIT_INFO(irq, 0, PIPE_A_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_A);

drivers/gpu/drm/i915/gvt/interrupt.c

617

SET_BIT_INFO(irq, 0, PIPE_B_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_B);

drivers/gpu/drm/i915/gvt/interrupt.c

618

SET_BIT_INFO(irq, 0, PIPE_C_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_C);

drivers/gpu/drm/i915/gvt/interrupt.c

621

SET_BIT_INFO(irq, 0, AUX_CHANNEL_A, INTEL_GVT_IRQ_INFO_DE_PORT);

drivers/gpu/drm/i915/gvt/interrupt.c

622

SET_BIT_INFO(irq, 3, DP_A_HOTPLUG, INTEL_GVT_IRQ_INFO_DE_PORT);

drivers/gpu/drm/i915/gvt/interrupt.c

625

SET_BIT_INFO(irq, 0, GSE, INTEL_GVT_IRQ_INFO_DE_MISC);

drivers/gpu/drm/i915/gvt/interrupt.c

628

SET_BIT_INFO(irq, 17, GMBUS, INTEL_GVT_IRQ_INFO_PCH);

drivers/gpu/drm/i915/gvt/interrupt.c

629

SET_BIT_INFO(irq, 19, CRT_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);

drivers/gpu/drm/i915/gvt/interrupt.c

630

SET_BIT_INFO(irq, 21, DP_B_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);

drivers/gpu/drm/i915/gvt/interrupt.c

631

SET_BIT_INFO(irq, 22, DP_C_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);

drivers/gpu/drm/i915/gvt/interrupt.c

632

SET_BIT_INFO(irq, 23, DP_D_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);

drivers/gpu/drm/i915/gvt/interrupt.c

635

SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_PCH);

drivers/gpu/drm/i915/gvt/interrupt.c

636

SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_PCH);

drivers/gpu/drm/i915/gvt/interrupt.c

637

SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_PCH);

drivers/gpu/drm/i915/gvt/interrupt.c

639

SET_BIT_INFO(irq, 4, PRIMARY_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);

drivers/gpu/drm/i915/gvt/interrupt.c

640

SET_BIT_INFO(irq, 5, SPRITE_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);

drivers/gpu/drm/i915/gvt/interrupt.c

642

SET_BIT_INFO(irq, 4, PRIMARY_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);

drivers/gpu/drm/i915/gvt/interrupt.c

643

SET_BIT_INFO(irq, 5, SPRITE_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);

drivers/gpu/drm/i915/gvt/interrupt.c

645

SET_BIT_INFO(irq, 4, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);

drivers/gpu/drm/i915/gvt/interrupt.c

646

SET_BIT_INFO(irq, 5, SPRITE_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);

drivers/gpu/drm/i915/gvt/interrupt.c

648

SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_DE_PORT);

drivers/gpu/drm/i915/gvt/interrupt.c

649

SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_DE_PORT);

drivers/gpu/drm/i915/gvt/interrupt.c

650

SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_DE_PORT);

drivers/gpu/drm/i915/gvt/interrupt.c

652

SET_BIT_INFO(irq, 3, PRIMARY_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);

drivers/gpu/drm/i915/gvt/interrupt.c

653

SET_BIT_INFO(irq, 3, PRIMARY_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);

drivers/gpu/drm/i915/gvt/interrupt.c

654

SET_BIT_INFO(irq, 3, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);

drivers/gpu/drm/i915/gvt/interrupt.c

656

SET_BIT_INFO(irq, 4, SPRITE_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);

drivers/gpu/drm/i915/gvt/interrupt.c

657

SET_BIT_INFO(irq, 4, SPRITE_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);

drivers/gpu/drm/i915/gvt/interrupt.c

658

SET_BIT_INFO(irq, 4, SPRITE_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);

drivers/gpu/drm/i915/gvt/interrupt.c

662

SET_BIT_INFO(irq, 24, PCU_THERMAL, INTEL_GVT_IRQ_INFO_PCU);

drivers/gpu/drm/i915/gvt/interrupt.c

663

SET_BIT_INFO(irq, 25, PCU_PCODE2DRIVER_MAILBOX, INTEL_GVT_IRQ_INFO_PCU);