SI
{"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
{"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
{"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
{"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
{"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
{"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
{"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
{"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
{"tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
{"tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
{"tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
{"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
{"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
{"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
{"tdui", OPTO(2,TOU), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
{"tdi", OP(2), OP_MASK, PPC64, PPCVLE, {TO, RA, SI}},
{"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
{"tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
{"twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
{"tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
{"tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
{"teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
{"twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
{"tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
{"twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
{"tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
{"twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
{"tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
{"twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
{"tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
{"twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
{"tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
{"twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
{"tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
{"twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
{"tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
{"twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
{"tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
{"twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
{"tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
{"twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
{"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
{"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
{"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
{"twui", OPTO(3,TOU), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
{"tui", OPTO(3,TOU), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
{"twi", OP(3), OP_MASK, PPCCOM, PPCVLE, {TO, RA, SI}},
{"ti", OP(3), OP_MASK, PWRCOM, PPCVLE, {TO, RA, SI}},
{"mulli", OP(7), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
{"muli", OP(7), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
{"subfic", OP(8), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
{"sfi", OP(8), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
{"dozi", OP(9), OP_MASK, M601, PPCVLE, {RT, RA, SI}},
{"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, SI}},
{"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, SI}},
{"cmpi", OP(11), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, SI}},
{"cmpi", OP(11), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, SI}},
{"addic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
{"ai", OP(12), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
{"addic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
{"ai.", OP(13), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
{"li", OP(14), DRA_MASK, PPCCOM, PPCVLE, {RT, SI}},
{"lil", OP(14), DRA_MASK, PWRCOM, PPCVLE, {RT, SI}},
{"addi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SI}},
#define SISIGNOPT SI + 1
{"e_add16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, SI}},
R(SI);
R(SI);
PUTREG(SI, si);
GETREG(SI, si);
{ PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
{ PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
{ PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
{ PCI_VDEVICE(SI, 0x5513), }, /* SiS 5513 */
{ PCI_VDEVICE(SI, 0x5518), }, /* SiS 5518 */
{ PCI_VDEVICE(SI, 0x1180), }, /* SiS 1180 */
{ PCI_VDEVICE(SI, 0x0180), sis_180 }, /* SiS 964/180 */
{ PCI_VDEVICE(SI, 0x0181), sis_180 }, /* SiS 964/180 */
{ PCI_VDEVICE(SI, 0x0182), sis_180 }, /* SiS 965/965L */
{ PCI_VDEVICE(SI, 0x0183), sis_180 }, /* SiS 965/965L */
{ PCI_VDEVICE(SI, 0x1182), sis_180 }, /* SiS 966/680 */
{ PCI_VDEVICE(SI, 0x1183), sis_180 }, /* SiS 966/966L/968/680 */
LUTON_P(14, SI, PHY_LED);
LUTON_P(15, SI, PHY_LED);
LUTON_P(16, SI, PHY_LED);
SERVAL_P(8, SI, NONE, NONE);
SERVAL_P(9, SI, MD, NONE);
SERVAL_P(10, SI, MD, NONE);
OCELOT_P(8, SI, TWI_SCL_M, IRQ0_OUT);
OCELOT_P(9, SI, TWI_SCL_M, IRQ1_OUT);
OCELOT_P(16, TWI, NONE, SI);
OCELOT_P(17, TWI, TWI_SCL_M, SI);
JAGUAR2_P(16, SI, TWI_SCL_M);
JAGUAR2_P(17, SI, TWI_SCL_M);
JAGUAR2_P(18, SI, TWI_SCL_M);
JAGUAR2_P(25, UART2, SI);
JAGUAR2_P(26, PTP2, SI);
JAGUAR2_P(27, PTP3, SI);
JAGUAR2_P(28, TWI2, SI);
JAGUAR2_P(29, TWI2, SI);
JAGUAR2_P(30, SG2, SI);
JAGUAR2_P(31, SG2, SI);
JAGUAR2_P(32, SG2, SI);
JAGUAR2_P(33, SG2, SI);
JAGUAR2_P(49, SFP, SI);
JAGUAR2_P(50, SFP, SI);
JAGUAR2_P(51, SFP, SI);
SERVALT_P(8, SI, SFP, TWI_SCL_M);
SERVALT_P(9, PCI_WAKE, SFP, SI);
SERVALT_P(14, REF_CLK, IRQ0_OUT, SI);
SERVALT_P(15, REF_CLK, IRQ1_OUT, SI);
SERVALT_P(16, TACHO, SFP, SI);
SERVALT_P(18, PTP2, SFP, SI);
SERVALT_P(19, PTP3, SFP, SI);
SERVALT_P(20, UART2, SFP, SI);
SERVALT_P(26, TWI_SCL_M, SFP, SI);
SERVALT_P(27, TWI_SCL_M, SFP, SI);
SERVALT_P(28, TWI_SCL_M, SFP, SI);
SPARX5_P(16, SI, TWI_SCL_M, SFP);
SPARX5_P(17, SI, TWI_SCL_M, SFP);
SPARX5_P(18, SI, TWI_SCL_M, SFP);
SPARX5_P(25, PTP3, SI, TWI_SCL_M);
SPARX5_P(26, UART2, SI, TWI_SCL_M);
SPARX5_P(27, UART2, SI, TWI_SCL_M);
SPARX5_P(28, TWI2, SI, SFP);
SPARX5_P(29, TWI2, SI, SFP);
SPARX5_P(30, SG2, SI, PWM);
SPARX5_P(31, SG2, SI, TWI_SCL_M);
SPARX5_P(32, SG2, SI, TWI_SCL_M);
SPARX5_P(33, SG2, SI, SFP);
SPARX5_P(44, SI, SFP, EMMC);
SPARX5_P(45, SI, SFP, EMMC);
SPARX5_P(48, TWI3, SI, SFP);
SPARX5_P(51, SFP, SI, TWI_SCL_M);
#define SI 0x04 /* Sequence Initiative */
cmd->un.genreq64.w5.hcsw.Fctl = (SI | LA);
typedef int SItype __attribute__((mode(SI)));
typedef unsigned int USItype __attribute__((mode(SI)));
typedef int SItype __attribute__ ((mode(SI)));
typedef unsigned int USItype __attribute__ ((mode(SI)));
#define INIT SI
{ PCI_VDEVICE(SI, 0x7502), .driver_data = AZX_DRIVER_SIS },
{ PCI_VDEVICE(SI, 0x7012), DEVICE_SIS }, /* SI7012 */
{ PCI_VDEVICE(SI, 0x7013), DEVICE_SIS }, /* SI7013 */