arch/riscv/include/asm/insn.h

412

#define SET_RD(insn, regs, val) (*REG_PTR(insn, SH_RD, regs) = (val))

arch/riscv/include/asm/insn.h

452

#define RVC_RS1S(insn) (8 + RV_X(insn, SH_RD, 3))

arch/riscv/kernel/traps_misaligned.c

268

insn = RVC_RS2S(insn) << SH_RD;

arch/riscv/kernel/traps_misaligned.c

270

((insn >> SH_RD) & 0x1f)) {

arch/riscv/kernel/traps_misaligned.c

277

insn = RVC_RS2S(insn) << SH_RD;

arch/riscv/kernel/traps_misaligned.c

279

((insn >> SH_RD) & 0x1f)) {

arch/riscv/kernel/traps_misaligned.c

285

insn = RVC_RS2S(insn) << SH_RD;

arch/riscv/kernel/traps_misaligned.c

293

insn = RVC_RS2S(insn) << SH_RD;

arch/riscv/kernel/traps_misaligned.c

300

insn = RVC_RS2S(insn) << SH_RD;

arch/riscv/kernel/traps_misaligned.c

304

insn = RVC_RS2S(insn) << SH_RD;

arch/riscv/kvm/vcpu_insn.c

137

if ((insn >> SH_RD) & MASK_RX)

arch/riscv/kvm/vcpu_insn.c

435

insn = RVC_RS2S(insn) << SH_RD;

arch/riscv/kvm/vcpu_insn.c

437

((insn >> SH_RD) & 0x1f)) {

arch/riscv/kvm/vcpu_insn.c

444

insn = RVC_RS2S(insn) << SH_RD;

arch/riscv/kvm/vcpu_insn.c

446

((insn >> SH_RD) & 0x1f)) {

arch/riscv/kvm/vcpu_insn.c

555

((insn >> SH_RD) & 0x1f)) {

arch/riscv/kvm/vcpu_insn.c

563

((insn >> SH_RD) & 0x1f)) {