Symbol: SH_CLK_MSTP32
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
126
SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
129
SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
142
[HWBLK_URAM] = SH_CLK_MSTP32(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
143
[HWBLK_XYMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
144
[HWBLK_TMU] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
145
[HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
146
[HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
147
[HWBLK_FLCTL] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
148
[HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
149
[HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
150
[HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
152
[HWBLK_IIC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
153
[HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 8, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
155
[HWBLK_SDHI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
156
[HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR2, 14, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
157
[HWBLK_USBF] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
158
[HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 9, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
159
[HWBLK_SIU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 8, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
160
[HWBLK_JPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
161
[HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
162
[HWBLK_BEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
163
[HWBLK_CEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
164
[HWBLK_VEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
165
[HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
166
[HWBLK_LCDC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 0, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
143
[HWBLK_TLB] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
144
[HWBLK_IC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
145
[HWBLK_OC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
146
[HWBLK_L2C] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
147
[HWBLK_ILMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 27, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
148
[HWBLK_FPU] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 24, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
149
[HWBLK_INTC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 22, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
150
[HWBLK_DMAC0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 21, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
151
[HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 20, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
152
[HWBLK_HUDI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
153
[HWBLK_UBC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 17, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
154
[HWBLK_TMU0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
155
[HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
156
[HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
157
[HWBLK_DMAC1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 12, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
158
[HWBLK_TMU1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
159
[HWBLK_FLCTL] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
160
[HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
161
[HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
162
[HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
163
[HWBLK_SCIF3] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 6, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
164
[HWBLK_SCIF4] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 5, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
165
[HWBLK_SCIF5] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 4, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
166
[HWBLK_MSIOF0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 2, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
167
[HWBLK_MSIOF1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 1, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
168
[HWBLK_MERAM] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 0, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
170
[HWBLK_IIC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
171
[HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 8, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
173
[HWBLK_ATAPI] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR2, 28, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
174
[HWBLK_ADC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 27, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
175
[HWBLK_TPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 25, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
176
[HWBLK_IRDA] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
177
[HWBLK_TSIF] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 22, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
178
[HWBLK_ICB] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 21, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
179
[HWBLK_SDHI0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 18, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
180
[HWBLK_SDHI1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 17, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
181
[HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR2, 14, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
182
[HWBLK_USB] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 11, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
183
[HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 10, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
184
[HWBLK_SIU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 8, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
185
[HWBLK_VEU2H1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
186
[HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
187
[HWBLK_BEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
188
[HWBLK_CEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
189
[HWBLK_VEU2H0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
190
[HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
191
[HWBLK_LCDC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
203
[HWBLK_TLB] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
204
[HWBLK_IC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
205
[HWBLK_OC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
206
[HWBLK_RSMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
207
[HWBLK_ILMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 27, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
208
[HWBLK_L2C] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
209
[HWBLK_FPU] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 24, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
210
[HWBLK_INTC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
211
[HWBLK_DMAC0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 21, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
212
[HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 20, CLK_ENABLE_ON_INIT),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
213
[HWBLK_HUDI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
214
[HWBLK_UBC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 17, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
215
[HWBLK_TMU0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
216
[HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
217
[HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
218
[HWBLK_DMAC1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 12, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
219
[HWBLK_TMU1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
220
[HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
221
[HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
222
[HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
223
[HWBLK_SCIF3] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 6, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
224
[HWBLK_SCIF4] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 5, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
225
[HWBLK_SCIF5] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 4, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
226
[HWBLK_MSIOF0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 2, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
227
[HWBLK_MSIOF1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 1, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
229
[HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 12, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
230
[HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 11, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
231
[HWBLK_IIC0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
232
[HWBLK_IIC1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 8, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
234
[HWBLK_MMC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 29, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
235
[HWBLK_ETHER] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 28, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
236
[HWBLK_ATAPI] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 26, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
237
[HWBLK_TPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 25, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
238
[HWBLK_IRDA] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
239
[HWBLK_TSIF] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 22, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
240
[HWBLK_USB1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 21, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
241
[HWBLK_USB0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 20, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
242
[HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 19, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
243
[HWBLK_SDHI0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 18, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
244
[HWBLK_SDHI1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 17, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
245
[HWBLK_VEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 15, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
246
[HWBLK_CEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 13, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
247
[HWBLK_BEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 12, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
248
[HWBLK_2DDMAC] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR2, 10, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
249
[HWBLK_SPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 9, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
250
[HWBLK_JPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
251
[HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
252
[HWBLK_BEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
253
[HWBLK_CEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
254
[HWBLK_VEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
255
[HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
256
[HWBLK_LCDC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
126
[MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
127
[MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
128
[MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
129
[MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
130
[MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
131
[MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
132
[MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
133
[MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
134
[MSTP019] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
135
[MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
136
[MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
137
[MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
138
[MSTP012] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 12, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
139
[MSTP011] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
140
[MSTP010] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
141
[MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
142
[MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
143
[MSTP007] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
146
[MSTP115] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 15, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
147
[MSTP114] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 14, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
148
[MSTP111] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 11, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
149
[MSTP109] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
150
[MSTP108] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 8, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
151
[MSTP107] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 7, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
152
[MSTP106] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 6, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
153
[MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
154
[MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 0, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
157
[MSTP331] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 31, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
158
[MSTP330] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 30, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
159
[MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 23, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
160
[MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
161
[MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
162
[MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
163
[MSTP319] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 19, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
164
[MSTP318] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 18, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
165
[MSTP317] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 17, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
166
[MSTP316] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 16, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
167
[MSTP315] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 15, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
168
[MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 14, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
169
[MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 13, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
170
[MSTP312] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 12, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
171
[MSTP304] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 4, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
172
[MSTP303] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 3, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
173
[MSTP302] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 2, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
174
[MSTP301] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 1, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
175
[MSTP300] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 0, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7757.c
85
[MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7757.c
86
[MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7757.c
89
[MSTP127] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 27, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7757.c
90
[MSTP114] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 14, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7757.c
91
[MSTP113] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 13, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7757.c
92
[MSTP112] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 12, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7757.c
93
[MSTP111] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 11, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7757.c
94
[MSTP110] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 10, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7757.c
95
[MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7757.c
96
[MSTP102] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 2, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7757.c
99
[MSTP220] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 20, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
100
[MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
101
[MSTP013] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 13, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
102
[MSTP012] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 12, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
103
[MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
104
[MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
105
[MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
106
[MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
109
[MSTP119] = SH_CLK_MSTP32(NULL, MSTPCR1, 19, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
110
[MSTP117] = SH_CLK_MSTP32(NULL, MSTPCR1, 17, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
111
[MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
112
[MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
113
[MSTP100] = SH_CLK_MSTP32(NULL, MSTPCR1, 0, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
91
[MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
92
[MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
93
[MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
94
[MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
95
[MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
96
[MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
97
[MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
98
[MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
99
[MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
100
[MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
101
[MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
102
[MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
103
[MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
104
[MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
105
[MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
106
[MSTP011] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
107
[MSTP010] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
108
[MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
109
[MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
110
[MSTP005] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
111
[MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
112
[MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
115
[MSTP112] = SH_CLK_MSTP32(NULL, MSTPCR1, 12, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
116
[MSTP110] = SH_CLK_MSTP32(NULL, MSTPCR1, 10, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
117
[MSTP109] = SH_CLK_MSTP32(NULL, MSTPCR1, 9, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
118
[MSTP108] = SH_CLK_MSTP32(NULL, MSTPCR1, 8, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
119
[MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
120
[MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
121
[MSTP103] = SH_CLK_MSTP32(NULL, MSTPCR1, 3, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
122
[MSTP102] = SH_CLK_MSTP32(NULL, MSTPCR1, 2, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
92
[MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
93
[MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
94
[MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
95
[MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
96
[MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
97
[MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
98
[MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
99
[MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
arch/sh/kernel/cpu/sh4a/clock-shx3.c
83
[MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
arch/sh/kernel/cpu/sh4a/clock-shx3.c
84
[MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
arch/sh/kernel/cpu/sh4a/clock-shx3.c
85
[MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
arch/sh/kernel/cpu/sh4a/clock-shx3.c
86
[MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
arch/sh/kernel/cpu/sh4a/clock-shx3.c
87
[MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
arch/sh/kernel/cpu/sh4a/clock-shx3.c
88
[MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
arch/sh/kernel/cpu/sh4a/clock-shx3.c
89
[MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
arch/sh/kernel/cpu/sh4a/clock-shx3.c
90
[MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
arch/sh/kernel/cpu/sh4a/clock-shx3.c
91
[MSTP001] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 1, 0),
arch/sh/kernel/cpu/sh4a/clock-shx3.c
92
[MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0),
arch/sh/kernel/cpu/sh4a/clock-shx3.c
95
[MSTP119] = SH_CLK_MSTP32(NULL, MSTPCR1, 19, 0),
arch/sh/kernel/cpu/sh4a/clock-shx3.c
96
[MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
arch/sh/kernel/cpu/sh4a/clock-shx3.c
97
[MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),