SH_CLK_DIV4
SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
SH_CLK_DIV4(&pll_clk, FRQCR, _bit, _mask, _flags)
SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)