drivers/clk/renesas/r9a07g043-cpg.c

21

#define SEL_SDHI0 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 0, 2)

drivers/clk/renesas/r9a07g043-cpg.c

22

#define SEL_SDHI1 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 4, 2)

drivers/clk/renesas/r9a07g043-cpg.c

25

#define SEL_SDHI0_STS SEL_PLL_PACK(CPG_CLKSTATUS, 28, 1)

drivers/clk/renesas/r9a07g043-cpg.c

26

#define SEL_SDHI1_STS SEL_PLL_PACK(CPG_CLKSTATUS, 29, 1)

drivers/clk/renesas/r9a07g044-cpg.c

22

#define SEL_SDHI0 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 0, 2)

drivers/clk/renesas/r9a07g044-cpg.c

23

#define SEL_SDHI1 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 4, 2)

drivers/clk/renesas/r9a07g044-cpg.c

26

#define SEL_SDHI0_STS SEL_PLL_PACK(CPG_CLKSTATUS, 28, 1)

drivers/clk/renesas/r9a07g044-cpg.c

27

#define SEL_SDHI1_STS SEL_PLL_PACK(CPG_CLKSTATUS, 29, 1)

drivers/clk/renesas/r9a08g045-cpg.c

41

#define G3S_SEL_PLL4_STS SEL_PLL_PACK(G3S_CLKSELSTATUS, 6, 1)

drivers/clk/renesas/r9a08g045-cpg.c

42

#define G3S_SEL_SDHI0_STS SEL_PLL_PACK(G3S_CLKSELSTATUS, 16, 1)

drivers/clk/renesas/r9a08g045-cpg.c

43

#define G3S_SEL_SDHI1_STS SEL_PLL_PACK(G3S_CLKSELSTATUS, 17, 1)

drivers/clk/renesas/r9a08g045-cpg.c

44

#define G3S_SEL_SDHI2_STS SEL_PLL_PACK(G3S_CLKSELSTATUS, 18, 1)

drivers/clk/renesas/r9a08g045-cpg.c

47

#define G3S_SEL_PLL4 SEL_PLL_PACK(G3S_CPG_PLL_DSEL, 6, 1)

drivers/clk/renesas/r9a08g045-cpg.c

48

#define G3S_SEL_SDHI0 SEL_PLL_PACK(G3S_CPG_SDHI_DSEL, 0, 2)

drivers/clk/renesas/r9a08g045-cpg.c

49

#define G3S_SEL_SDHI1 SEL_PLL_PACK(G3S_CPG_SDHI_DSEL, 4, 2)

drivers/clk/renesas/r9a08g045-cpg.c

50

#define G3S_SEL_SDHI2 SEL_PLL_PACK(G3S_CPG_SDHI_DSEL, 8, 2)

drivers/clk/renesas/r9a08g046-cpg.c

66

#define G3L_SEL_ETH0_TX SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 0, 1)

drivers/clk/renesas/r9a08g046-cpg.c

67

#define G3L_SEL_ETH0_RX SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 1, 1)

drivers/clk/renesas/r9a08g046-cpg.c

68

#define G3L_SEL_ETH0_RM SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 2, 1)

drivers/clk/renesas/r9a08g046-cpg.c

69

#define G3L_SEL_ETH0_CLK_TX_I SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 3, 1)

drivers/clk/renesas/r9a08g046-cpg.c

70

#define G3L_SEL_ETH0_CLK_RX_I SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 4, 1)

drivers/clk/renesas/r9a08g046-cpg.c

71

#define G3L_SEL_ETH1_TX SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 8, 1)

drivers/clk/renesas/r9a08g046-cpg.c

72

#define G3L_SEL_ETH1_RX SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 9, 1)

drivers/clk/renesas/r9a08g046-cpg.c

73

#define G3L_SEL_ETH1_RM SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 10, 1)

drivers/clk/renesas/r9a08g046-cpg.c

74

#define G3L_SEL_ETH1_CLK_TX_I SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 11, 1)

drivers/clk/renesas/r9a08g046-cpg.c

75

#define G3L_SEL_ETH1_CLK_RX_I SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 12, 1)

drivers/clk/renesas/r9a08g046-cpg.c

76

#define G3L_SEL_RSCI0 SEL_PLL_PACK(G3L_CPG_RSCI_SSEL, 0, 2)

drivers/clk/renesas/r9a08g046-cpg.c

77

#define G3L_SEL_RSCI1 SEL_PLL_PACK(G3L_CPG_RSCI_SSEL, 2, 2)

drivers/clk/renesas/r9a08g046-cpg.c

78

#define G3L_SEL_RSCI2 SEL_PLL_PACK(G3L_CPG_RSCI_SSEL, 4, 2)

drivers/clk/renesas/r9a08g046-cpg.c

79

#define G3L_SEL_RSCI3 SEL_PLL_PACK(G3L_CPG_RSCI_SSEL, 6, 2)

drivers/clk/renesas/r9a08g046-cpg.c

80

#define G3L_SEL_RSPI0 SEL_PLL_PACK(G3L_CPG_RSPI_SSEL, 0, 2)

drivers/clk/renesas/r9a08g046-cpg.c

81

#define G3L_SEL_RSPI1 SEL_PLL_PACK(G3L_CPG_RSPI_SSEL, 2, 2)

drivers/clk/renesas/r9a08g046-cpg.c

82

#define G3L_SEL_RSPI2 SEL_PLL_PACK(G3L_CPG_RSPI_SSEL, 4, 2)

drivers/clk/renesas/r9a09g011-cpg.c

25

#define SEL_B SEL_PLL_PACK(0x214, 0, 1)

drivers/clk/renesas/r9a09g011-cpg.c

26

#define SEL_CSI0 SEL_PLL_PACK(0x330, 0, 1)

drivers/clk/renesas/r9a09g011-cpg.c

27

#define SEL_CSI4 SEL_PLL_PACK(0x330, 4, 1)

drivers/clk/renesas/r9a09g011-cpg.c

28

#define SEL_D SEL_PLL_PACK(0x214, 1, 1)

drivers/clk/renesas/r9a09g011-cpg.c

29

#define SEL_E SEL_PLL_PACK(0x214, 2, 1)

drivers/clk/renesas/r9a09g011-cpg.c

30

#define SEL_SDI SEL_PLL_PACK(0x300, 0, 1)

drivers/clk/renesas/r9a09g011-cpg.c

31

#define SEL_W0 SEL_PLL_PACK(0x32C, 0, 1)

drivers/clk/renesas/rzg2l-cpg.h

78

#define SEL_PLL3_3 SEL_PLL_PACK(CPG_PL3_SSEL, 8, 1)

drivers/clk/renesas/rzg2l-cpg.h

79

#define SEL_PLL5_4 SEL_PLL_PACK(CPG_OTHERFUNC1_REG, 0, 1)

drivers/clk/renesas/rzg2l-cpg.h

80

#define SEL_PLL6_2 SEL_PLL_PACK(CPG_PL6_ETH_SSEL, 0, 1)

drivers/clk/renesas/rzg2l-cpg.h

81

#define SEL_GPU2 SEL_PLL_PACK(CPG_PL6_SSEL, 12, 1)