SET_REG
writel_relaxed(BM_C0_EN, priv.base + HW_TCR + SET_REG);
priv.base + HW_MCR + SET_REG);
writel_relaxed(BM_C0_EN, priv.base + HW_TCR + SET_REG);
writel_relaxed(BM_C1_EN, priv.base + HW_TCR + SET_REG);
+ SET_REG)
icoll_intr_reg(d) + SET_REG);
icoll_priv.intr + SET_REG + HW_ICOLL_INTERRUPTn(d->hwirq));
SET_REG(DISTXFIFO, cmd->msg[i]);
SET_REG(DISTXFIFO, value);
SET_REG(UPLCCST0, 0xe0);
writel_relaxed(val, addr + SET_REG);
SET_REG(codec, SI3054_LINE_RATE, substream->runtime->rate);
SET_REG(codec, SI3054_LINE_LEVEL, val);
SET_REG(codec, SI3054_LINE_RATE, 9600);
SET_REG(codec, SI3054_LINE_LEVEL, SI3054_DTAG_MASK|SI3054_ATAG_MASK);
SET_REG(codec, SI3054_EXTENDED_MID, 0);
SET_REG(codec, SI3054_GPIO_POLARITY, 0xffff);
SET_REG(codec, SI3054_GPIO_CFG, 0x0);
SET_REG(codec, SI3054_MISC_AFE, 0);
SET_REG(codec, SI3054_LINE_CFG1,0x200);