Symbol: SFB
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
159
SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
160
SFB(blk, GRPH_CONTROL, GRPH_BANK_WIDTH, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
161
SFB(blk, GRPH_CONTROL, GRPH_BANK_HEIGHT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
162
SFB(blk, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
163
SFB(blk, GRPH_CONTROL, GRPH_TILE_SPLIT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
164
SFB(blk, GRPH_CONTROL, GRPH_PIPE_CONFIG, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
165
SFB(blk, GRPH_CONTROL, GRPH_ARRAY_MODE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
166
SFB(blk, GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE, mask_sh)
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
170
SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
171
SFB(blk, GRPH_CONTROL, GRPH_BANK_WIDTH, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
172
SFB(blk, GRPH_CONTROL, GRPH_BANK_HEIGHT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
173
SFB(blk, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
174
SFB(blk, GRPH_CONTROL, GRPH_TILE_SPLIT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
175
SFB(blk, GRPH_CONTROL, GRPH_MICRO_TILE_MODE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
176
SFB(blk, GRPH_CONTROL, GRPH_PIPE_CONFIG, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
177
SFB(blk, GRPH_CONTROL, GRPH_ARRAY_MODE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
178
SFB(blk, GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE, mask_sh)
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
181
SFB(blk, GRPH_ENABLE, GRPH_ENABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
182
SFB(blk, GRPH_CONTROL, GRPH_DEPTH, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
183
SFB(blk, GRPH_CONTROL, GRPH_FORMAT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
184
SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
185
SFB(blk, GRPH_X_START, GRPH_X_START, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
186
SFB(blk, GRPH_Y_START, GRPH_Y_START, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
187
SFB(blk, GRPH_X_END, GRPH_X_END, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
188
SFB(blk, GRPH_Y_END, GRPH_Y_END, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
189
SFB(blk, GRPH_PITCH, GRPH_PITCH, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
190
SFB(blk, HW_ROTATION, GRPH_ROTATION_ANGLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
191
SFB(blk, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
192
SFB(blk, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
193
SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_SELECT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
194
SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_R_SIGN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
195
SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_G_SIGN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
196
SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_B_SIGN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
197
SFB(blk, GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
198
SFB(blk, GRPH_SECONDARY_SURFACE_ADDRESS, GRPH_SECONDARY_SURFACE_ADDRESS, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
199
SFB(blk, GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
200
SFB(blk, GRPH_PRIMARY_SURFACE_ADDRESS, GRPH_PRIMARY_SURFACE_ADDRESS, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
201
SFB(blk, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
202
SFB(blk, GRPH_UPDATE, GRPH_UPDATE_LOCK, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
203
SFB(blk, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_H_RETRACE_EN, mask_sh)
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
207
SFB(blk, GRPH_ENABLE, GRPH_ENABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
208
SFB(blk, GRPH_CONTROL, GRPH_DEPTH, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
209
SFB(blk, GRPH_CONTROL, GRPH_FORMAT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
210
SFB(blk, GRPH_X_START, GRPH_X_START, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
211
SFB(blk, GRPH_Y_START, GRPH_Y_START, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
212
SFB(blk, GRPH_X_END, GRPH_X_END, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
213
SFB(blk, GRPH_Y_END, GRPH_Y_END, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
214
SFB(blk, GRPH_PITCH, GRPH_PITCH, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
215
SFB(blk, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
216
SFB(blk, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
217
SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_SELECT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
218
SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_R_SIGN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
219
SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_G_SIGN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
220
SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_B_SIGN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
221
SFB(blk, GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
222
SFB(blk, GRPH_SECONDARY_SURFACE_ADDRESS, GRPH_SECONDARY_SURFACE_ADDRESS, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
223
SFB(blk, GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
224
SFB(blk, GRPH_PRIMARY_SURFACE_ADDRESS, GRPH_PRIMARY_SURFACE_ADDRESS, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
225
SFB(blk, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
226
SFB(blk, GRPH_UPDATE, GRPH_UPDATE_LOCK, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
227
SFB(blk, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_H_RETRACE_EN, mask_sh)
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
231
SFB(blk, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, mask_sh)
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
234
SFB(blk, DVMM_PTE_CONTROL, DVMM_PAGE_WIDTH, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
235
SFB(blk, DVMM_PTE_CONTROL, DVMM_PAGE_HEIGHT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
236
SFB(blk, DVMM_PTE_CONTROL, DVMM_MIN_PTE_BEFORE_FLIP, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
237
SFB(blk, DVMM_PTE_ARB_CONTROL, DVMM_PTE_REQ_PER_CHUNK, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
238
SFB(blk, DVMM_PTE_ARB_CONTROL, DVMM_MAX_PTE_REQ_OUTSTANDING, mask_sh)
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
242
SFB(blk, DPG_PIPE_ARBITRATION_CONTROL1, PIXEL_DURATION, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
243
SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
244
SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
245
SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
246
SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_IGNORE_FBC, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
251
SFB(blk, DPG_PIPE_ARBITRATION_CONTROL3, URGENCY_WATERMARK_MASK, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
252
SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
253
SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
254
SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
255
SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_ENABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
256
SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
257
SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
258
SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_WATERMARK, mask_sh)
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
268
SFB(blk, DPG_PIPE_ARBITRATION_CONTROL1, PIXEL_DURATION, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
269
SFB(blk, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
270
SFB(blk, DPG_WATERMARK_MASK_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
271
SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
272
SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
273
SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
274
SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_IGNORE_FBC, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
279
SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
280
SFB(blk, DPG_WATERMARK_MASK_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
281
SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_ENABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
282
SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
283
SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
284
SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_WATERMARK, mask_sh)
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
301
SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
302
SFB(blk, GRPH_CONTROL, GRPH_SW_MODE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
303
SFB(blk, GRPH_CONTROL, GRPH_SE_ENABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
304
SFB(blk, GRPH_CONTROL, GRPH_NUM_SHADER_ENGINES, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
305
SFB(blk, GRPH_CONTROL, GRPH_NUM_PIPES, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
306
SFB(blk, GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE, mask_sh)
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
309
SFB(blk, DPG_PIPE_STUTTER_CONTROL2, STUTTER_EXIT_SELF_REFRESH_WATERMARK, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
310
SFB(blk, DPG_PIPE_STUTTER_CONTROL2, STUTTER_ENTER_SELF_REFRESH_WATERMARK, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
311
SFB(blk, DPG_PIPE_URGENT_LEVEL_CONTROL, URGENT_LEVEL_LOW_WATERMARK, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
312
SFB(blk, DPG_PIPE_URGENT_LEVEL_CONTROL, URGENT_LEVEL_HIGH_WATERMARK, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
313
SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
314
SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
315
SFB(blk, DPG_WATERMARK_MASK_CONTROL, PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
316
SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_ENABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
317
SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
318
SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
319
SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_WATERMARK, mask_sh)