arch/powerpc/xmon/ppc-opc.c

2518

#define SE_RR_MASK SE_RR(0x3f, 3)

arch/powerpc/xmon/ppc-opc.c

6998

{"se_mr", SE_RR(0,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},

arch/powerpc/xmon/ppc-opc.c

6999

{"se_mtar", SE_RR(0,2), SE_RR_MASK, PPCVLE, 0, {ARX, RY}},

arch/powerpc/xmon/ppc-opc.c

7000

{"se_mfar", SE_RR(0,3), SE_RR_MASK, PPCVLE, 0, {RX, ARY}},

arch/powerpc/xmon/ppc-opc.c

7001

{"se_add", SE_RR(1,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},

arch/powerpc/xmon/ppc-opc.c

7002

{"se_mullw", SE_RR(1,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},

arch/powerpc/xmon/ppc-opc.c

7003

{"se_sub", SE_RR(1,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},

arch/powerpc/xmon/ppc-opc.c

7004

{"se_subf", SE_RR(1,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},

arch/powerpc/xmon/ppc-opc.c

7005

{"se_cmp", SE_RR(3,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},

arch/powerpc/xmon/ppc-opc.c

7006

{"se_cmpl", SE_RR(3,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},

arch/powerpc/xmon/ppc-opc.c

7007

{"se_cmph", SE_RR(3,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},

arch/powerpc/xmon/ppc-opc.c

7008

{"se_cmphl", SE_RR(3,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},

arch/powerpc/xmon/ppc-opc.c

7066

{"se_srw", SE_RR(16,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},

arch/powerpc/xmon/ppc-opc.c

7067

{"se_sraw", SE_RR(16,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},

arch/powerpc/xmon/ppc-opc.c

7068

{"se_slw", SE_RR(16,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},

arch/powerpc/xmon/ppc-opc.c

7069

{"se_nop", SE_RR(17,0), 0xffff, PPCVLE, 0, {0}},

arch/powerpc/xmon/ppc-opc.c

7070

{"se_or", SE_RR(17,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},

arch/powerpc/xmon/ppc-opc.c

7071

{"se_andc", SE_RR(17,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},

arch/powerpc/xmon/ppc-opc.c

7072

{"se_and", SE_RR(17,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},

arch/powerpc/xmon/ppc-opc.c

7073

{"se_and.", SE_RR(17,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},