SET_VAL
buf[j++] = SET_VAL(CLE_BR_DATA, br->data) |
SET_VAL(CLE_BR_MASK, br->mask);
*reg = SET_VAL(SB_IPFRAG, frag) |
SET_VAL(SB_IPPROT, type) |
SET_VAL(SB_IPVER, ver) |
SET_VAL(SB_HDRLEN, len);
*idt_reg = SET_VAL(IDT_DSTQID, dstqid) |
SET_VAL(IDT_FPSEL1, fpsel) |
SET_VAL(IDT_NFPSEL1, nfpsel);
*idt_reg = SET_VAL(IDT_DSTQID, dstqid) |
SET_VAL(IDT_FPSEL, fpsel) |
SET_VAL(IDT_NFPSEL, nfpsel);
buf[0] = SET_VAL(CLE_DROP, dbptr->drop);
buf[4] = SET_VAL(CLE_FPSEL, dbptr->fpsel) |
SET_VAL(CLE_NFPSEL, dbptr->nxtfpsel) |
SET_VAL(CLE_DSTQIDL, dbptr->dstqid);
buf[5] = SET_VAL(CLE_DSTQIDH, (u32)dbptr->dstqid >> CLE_DSTQIDL_LEN) |
SET_VAL(CLE_PRIORITY, dbptr->cle_priority);
buf[j++] = SET_VAL(CLE_TYPE, kn->node_type);
buf[j] = SET_VAL(CLE_KN_PRIO, key->priority) |
SET_VAL(CLE_KN_RPTR, key->result_pointer);
data = SET_VAL(CLE_KN_PRIO, key->priority) |
SET_VAL(CLE_KN_RPTR, key->result_pointer);
buf[j++] = SET_VAL(CLE_DN_TYPE, dn->node_type) |
SET_VAL(CLE_DN_LASTN, dn->last_node) |
SET_VAL(CLE_DN_HLS, dn->hdr_len_store) |
SET_VAL(CLE_DN_EXT, dn->hdr_extn) |
SET_VAL(CLE_DN_BSTOR, dn->byte_store) |
SET_VAL(CLE_DN_SBSTOR, dn->search_byte_store) |
SET_VAL(CLE_DN_RPTR, dn->result_pointer);
buf[j++] = SET_VAL(CLE_BR_VALID, br->valid) |
SET_VAL(CLE_BR_NPPTR, npp) |
SET_VAL(CLE_BR_JB, br->jump_bw) |
SET_VAL(CLE_BR_JR, br->jump_rel) |
SET_VAL(CLE_BR_OP, br->operation) |
SET_VAL(CLE_BR_NNODE, br->next_node) |
SET_VAL(CLE_BR_NBR, br->next_branch);
raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) |
SET_VAL(BUFDATALEN, hw_len) |
raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) |
SET_VAL(BUFDATALEN, bufdatalen) |
SET_VAL(FPQNUM, buf_pool->dst_ring_num) |
SET_VAL(STASH, 3));
*hopinfo |= SET_BIT(ET) | SET_VAL(MSS, mss_index);
*hopinfo |= SET_VAL(TCPHDR, l4hlen) |
SET_VAL(IPHDR, l3hlen) |
SET_VAL(ETHHDR, ethhdr) |
SET_VAL(EC, csum_enable) |
SET_VAL(IS, proto) |
desc[idx ^ 1] = cpu_to_le64(SET_VAL(DATAADDR, addr) |
SET_VAL(BUFDATALEN, len));
raw_desc->m3 = cpu_to_le64(SET_VAL(HENQNUM, tx_ring->dst_ring_num) |
raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) |
SET_VAL(BUFDATALEN, hw_len) |
exp_desc[2] = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) |
SET_VAL(LL_BYTES_MSB, i) |
SET_VAL(LL_LEN, idx));
raw_desc->m2 = cpu_to_le64(SET_VAL(LL_BYTES_LSB, ell_bytes));
raw_desc->m0 = cpu_to_le64(SET_VAL(LL, ll) | SET_VAL(NV, nv) |
SET_VAL(USERINFO, tx_ring->tail));
data = SET_VAL(X2_INTLINE, ring->id & RING_BUFNUM_MASK) |
ring_cfg[0] |= SET_VAL(X2_INTLINE, ring->id & RING_BUFNUM_MASK);
ring_cfg[0] |= SET_VAL(X2_CFGCRID, 2);
ring_cfg[2] |= QCOHERENT | SET_VAL(RINGADDRL, addr);
ring_cfg[3] |= SET_VAL(RINGSIZE, ring->cfgsize)
| SET_VAL(RINGADDRH, addr);
ring_cfg[4] |= SET_VAL(X2_SELTHRSH, 1);
ring_cfg[4] |= SET_VAL(X2_RINGTYPE, val);
ring_cfg[3] |= SET_VAL(RINGMODE, BUFPOOL_MODE);
ring_cfg[4] |= SET_VAL(X2_RECOMTIMEOUT, 0x7);
data = SET_VAL(TSO_MSS1, data >> TSO_MSS1_POS) |
SET_VAL(TSO_MSS0, mss);
data = SET_VAL(TSO_MSS1, mss) | SET_VAL(TSO_MSS0, data);
val = SET_VAL(PHY_ADDR, phy_id) | SET_VAL(REG_ADDR, reg);
val = SET_VAL(HSTPHYADX, phy_id) | SET_VAL(HSTREGADX, reg) |
SET_VAL(HSTMIIMWRDAT, data);
val = HSTLDCMD | SET_VAL(HSTMIIMCMD, MIIM_CMD_LEGACY_WRITE);
val = SET_VAL(HSTPHYADX, phy_id) | SET_VAL(HSTREGADX, reg);
val = HSTLDCMD | SET_VAL(HSTMIIMCMD, MIIM_CMD_LEGACY_READ);
data = SET_VAL(PHY_ADDR, phy_id) | SET_VAL(REG_ADDR, reg);
SET_VAL(AR9170_MAC_BCN_DTIM, v,
SET_VAL(AR9170_MAC_BCN_DTIM, v,
SET_VAL(AR9170_MAC_BCN_PERIOD, v, ar->global_beacon_int);
SET_VAL(AR9170_MAC_PRETBTT, pretbtt, ar->global_pretbtt);
SET_VAL(AR9170_MAC_PRETBTT2, pretbtt, ar->global_pretbtt);
SET_VAL(CARL9170FW_PHY_HT_EXT_CHAN_OFF, rf.ht_settings, offs);
SET_VAL(AR9170_PHY_SETTLING_SWITCH, val, m->switchSettling);
SET_VAL(AR9170_PHY_DESIRED_SZ_PGA, val, m->pgaDesiredSize);
SET_VAL(AR9170_PHY_DESIRED_SZ_ADC, val, m->adcDesiredSize);
SET_VAL(AR9170_PHY_RF_CTL4_TX_END_XPAB_OFF, val, m->txEndToXpaOff);
SET_VAL(AR9170_PHY_RF_CTL4_TX_END_XPAA_OFF, val, m->txEndToXpaOff);
SET_VAL(AR9170_PHY_RF_CTL4_FRAME_XPAB_ON, val, m->txFrameToXpaOn);
SET_VAL(AR9170_PHY_RF_CTL4_FRAME_XPAA_ON, val, m->txFrameToXpaOn);
SET_VAL(AR9170_PHY_RF_CTL3_TX_END_TO_A2_RX_ON, val, m->txEndToRxOn);
SET_VAL(AR9170_PHY_RXGAIN_TXRX_ATTEN, val, m->txRxAttenCh[0]);
SET_VAL(AR9170_PHY_RXGAIN_TXRX_ATTEN, val, m->txRxAttenCh[1]);
SET_VAL(AR9170_PHY_GAIN_2GHZ_RXTX_MARGIN, val, m->rxTxMarginCh[0]);
SET_VAL(AR9170_PHY_GAIN_2GHZ_BSW_MARGIN, val, m->bswMargin[0]);
SET_VAL(AR9170_PHY_GAIN_2GHZ_RXTX_MARGIN, val, m->rxTxMarginCh[1]);
SET_VAL(AR9170_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, val, m->iqCalICh[0]);
SET_VAL(AR9170_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, val, m->iqCalQCh[0]);
SET_VAL(AR9170_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, val, m->iqCalICh[1]);
SET_VAL(AR9170_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, val, m->iqCalQCh[1]);
SET_VAL(AR9170_PHY_TPCRG1_PD_GAIN_1, val,
SET_VAL(AR9170_PHY_TPCRG1_PD_GAIN_2, val,
SET_VAL(CARL9170_TX_SUPER_MISC_QUEUE, txc->s.misc, hw_queue);
SET_VAL(CARL9170_TX_SUPER_MISC_VIF_ID, txc->s.misc, cvif->id);
SET_VAL(CARL9170_TX_SUPER_AMPDU_DENSITY,
SET_VAL(CARL9170_TX_SUPER_AMPDU_FACTOR,
SET_VAL(CARL9170_TX_SUPER_MISC_QUEUE, q,
SET_VAL(AR9170_MAC_BCN_HT1_PWR_CTRL, *ht1, 7);
SET_VAL(AR9170_MAC_BCN_HT1_TPC, *ht1, power);
SET_VAL(AR9170_MAC_BCN_HT1_CHAIN_MASK, *ht1, chains);
SET_VAL(AR9170_MAC_BCN_HT2_LEN, *plcp, skb->len + FCS_LEN);
SET_VAL(AR9170_TX_PHY_MCS, phyrate, txrate->idx);
SET_VAL(CARL9170_TX_SUPER_RI_TRIES, txc->s.ri[i],