Symbol: SET_RD
arch/riscv/kernel/traps_misaligned.c
322
SET_RD(insn, regs, (long)(val.data_ulong << shift) >> shift);
arch/riscv/kvm/vcpu_insn.c
138
SET_RD(insn, &vcpu->arch.guest_context,
arch/riscv/kvm/vcpu_insn.c
651
SET_RD(insn, &vcpu->arch.guest_context,
arch/riscv/kvm/vcpu_insn.c
656
SET_RD(insn, &vcpu->arch.guest_context,
arch/riscv/kvm/vcpu_insn.c
661
SET_RD(insn, &vcpu->arch.guest_context,
arch/riscv/kvm/vcpu_insn.c
666
SET_RD(insn, &vcpu->arch.guest_context,